HD49343NPHNP_15 Datasheet, PDF (12/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Preliminary
 Calibration and Reset (D14, D15 of address 2)
By performing Software Reset and a calibration only once at the time of a power supply, a bias gap of an internal
circuit is canceled automatically. (Offset calibration) Please be sure to perform by this LSI.
An automatic offset calibration adjusts DC voltage of DAC added to the output of PGA amplifier.
The clamp data (56 LSB to 304 LSB) based on a register setup is added to the data which cancels output offset of
PGA amplifier and input offset of ADC, and it is given to this DAC.
Automatic offset calibration starts automatically after the Reset mode release by register setup, and it ends after
40000 (adclk). (In case of fclk = 20 MHz: 2.0 ms, In case of fclk = 10 MHz: 4.0 ms)
V_DD
SP1,2_in
ADCLK_in
OBP_in
Be stable in power supply voltage within the limits of operation.
The input pulse should be normal.
1 ms or more
A high-speed pulse should
the right phase
OBP is started in this period
OBP should the
right phase
Serial data transfer
Do not input OBP before Reset
2 ms or more
(Charge of external C)
40,000 adclk
(Offset calibration)
(1)
(2) (3) (4)
(5)
Reset_bit
Calb_bit
(H/L is unfixed
at the time of a
power supply on)
40,000adclk periods are
spent for adjustment.
It clears automatically
after 40,000adclk(s)
The contents of the above-mentioned serial data transmission are shown below.
Refer to the serial data specification table for the details of a register setup.
(1) Reset = 0, Calb = 0
: Reset bit = Transfer 0
It stands by 2 ms or more as charge time of an external capacitor.
(2) Reset = 1, Calb = 0
: Reset bit = Transfer 1 → All registers are initialized.
(3) All data transfer
: Transfer the resister which needs data changes.
(4) Calb = 1
: Automatic offset calibration is start. Standby time is 40,000 or more adclks.
(5) Transfer the changed data : Data, such as a PGA gain, to change is transmitted.
An address 2 is necessary to send after a calibration finishes,
please set as Reset = 1 and Calb = 1.
∗ Since it is necessary to decide SP1, SP2, and an ADCLK phase before transmitting Calb bit = 1,
please perform this work with input pulse is stabilized.
∗ When offset calibration is needed, please avoid the V.BLK period.
Figure 6 Operation Sequence of at Power ON
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
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