HD49343NPHNP_15 Datasheet, PDF (16/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Preliminary
• Horizontal timing
sp1
PBLK
OBP
5clk
CPDM
OB detection
(8/4clk)
cpdm_dl × 4(clk)
When it observes with a MON terminal,
CPDM is late 4clks.
2clk+setting value
ADC output
Signal
output
2clk
4clk detection _11clk
Clamp level
Signal output
Differential code standard
Notes: 1. Duty of CLK_in should be less than 50 ± 15%.
2. The rising edge of sp1 and the edge of PBLK should not overlap.
(Should not be within ±5ns.)
3. Each pulse is indicated on the basis of negative polarity.
4. CPDM cannot be made from a set without PBLK.
Figure 11 The Timing of H.BLK Period
• Vertical timing
PBLK
OBP
CPDM
Figure 12 The Timing of V.BLK Period
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
Page 16 of 22