HD49343NPHNP_15 Datasheet, PDF (21/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49343NP/HNP
Preliminary
Check Item
Please check following items for use.
No.
Item
1 Input pulse polarity
2 Input pulse timing
3 Output timing
4 Power supply voltage
5 Offset calibration
6 S/N improvement
7 Clamp operation
8 The notes about hardware
Contents
Are the polarity of OBP and PBLK and the polarity set as D11-D12 of
an address 2 match?
Do SP1 and SP2 keep the relation of Figure 14 and Table 4?
Note: Since especially tCDS5 becomes equivalent to frequency of
operation. Moreover, as for SP1 and SP2, a Low period
should not overlap.
Is the ADCLK rising set up near SP1 falling edge?
(Figure 14, Table 4)
Are an ADCLK rising and OBP falling edge separated 5 ns or more?
(Figure 9)
Is the margin for 5 ns or more in the edge of the ADCLK rising to
PBLK?
Is it satisfactory to an OBP phase and a CPDM phase?
(Figure 11 and 12)
Is a margin in the latch phase of an ADC output and DSP?
When using differential code, does not a standard signal phase have
a problem? (Figure 9 and 11)
When VRT voltage = 2.4 V are chosen, more than Vdd = 3.1 V is
required.
Is the offset calibration of Figure 6 performed at the time of a power
on?
Adjustment of SP1 and SP2 phase. Adjustment of an ADCLK phase.
When adjustment finishes, re-check about item 2.
Filter adjustment of LPF_sel, SHSW_fsel, and SHA_fsel.
The capacitor of FBC becomes the relation of a trade-off of high-
speed lead in of a horizontal line noise and a clamp. Please check
both characteristics and determine the optimal value.
A clamp mistake is made to induce and data and pulse timing of a
dummy clamp are set up. Please see a margin with the time of
alumnus clamp.
Take large Gnd as much as possible.
Please separate an analog power supply and a digital power supply
by L etc.
Please arrange an input pulse, a serial communication line, etc. not to
jump in to an analog part.
An ADC output is extended for a long time, or 30 MHz or more in
carrying out high-speed operation, it becomes easy to generate a
ripple. In such a case, feed in about 100  into 12 ADC output pins
as dumping resistance in series, or please try reduction using
differential code.
Judgment
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
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