SH72544R Datasheet, PDF (44/56 Pages) Renesas Technology Corp – Microcomputer Development Environment System

Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC,
and SH72531
7. If breaks occur immediately after executing non-delayed branch and TRAPA instructions and
generating a branch due to exception or interrupt, a trace for one branch will not be acquired
immediately before such breaks. However, this does not affect on generation of breaks caused
by a BREAKPOINT and a break before executing instructions of Event Condition.
8. For the result by software trace, a value in the [Data] item is not correct (that value is correct
for window trace).
9. The AUD trace function is not available if the target device is the SH72531FCC or SH72531.
10. The CPU clock ratios 1:1 and 1:2 cannot be used for the AUD clock (AUDCK) with the
SH72546RFCC, SH72544R, or SH72543R as the target device.
2.2.3 Notes on Using the JTAG (H-UDI) Clock (TCK)
1. Set the JTAG clock (TCK) frequency to lower than the frequency of the peripheral module
clock.
2. The initial value of the JTAG clock (TCK) is 10 MHz.
3. A value to be set for the JTAG clock (TCK) is initialized after executing [Reset CPU] or
[Reset Go]. Thus the TCK value will be the initial value.
2.2.4 Notes on Setting the [Breakpoint] Dialog Box
1. When an odd address is set, the next lowest even address is used.
2. A BREAKPOINT is accomplished by replacing instructions of the specified address.
It cannot be set to the following addresses:
⎯ An area other than CS and the internal RAM
⎯ An instruction in which Break Condition 2 is satisfied
⎯ A slot instruction of a delayed branch instruction
3. During step operation, specifying BREAKPOINTs and Event Condition breaks are disabled.
4. When execution resumes from the address where a BREAKPOINT is specified and a break
occurs before Event Condition execution, single-step operation is performed at the address
before execution resumes. Therefore, realtime operation cannot be performed.
5. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC
value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot
instruction of a delayed branch instruction.
6. If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area, a
mark z will be displayed in the [BP] area of the address on the [Source] or [Disassembly]
window by refreshing the [Memory] window, etc. after Go execution. However, no break will
Rev. 2.00 Jun. 08, 2009 Page 38 of 46
REJ10J1941-0200