HYB18H512321BF Datasheet, PDF (6/43 Pages) Qimonda AG – 512-Mbit GDDR3 Graphics RAM

Internet Data Sheet
2.1
Ball Definition and Description
HYB18H512321BF
512-Mbit GDDR3
TABLE 2
Ball Description
Ball
Type Detailed Function
CLK, CLK
CKE
CS
RAS, CAS,
WE
DQ<0:31>
DM<0:3>
RDQS<0:3>
WDQS<0:3>
BA<0:2>
Input
Input
Input
Input
I/O
Input
Output
Input
Input
Clock:
CLK and CLK are differential clock inputs. Address and command inputs are latched on the positive
edge of CLK. Graphics SDRAM outputs (RDQS, DQs) are referenced to CLK. CLK and CLK are not
internally terminated.
Clock Enable:
CKE HIGH activates and CKE LOW deactivates the internal clock and input buffers. Taking CKE
LOW provides Power Down. If all banks are precharged, this mode is called Precharge Power Down
and Self Refresh mode is entered if a Auto Refresh command is issued. If at least one bank is open,
Active Power Down mode is entered and no Self Refresh is allowed. All input receivers except CLK,
CLK and CKE are disabled during Power Down. In Self Refresh mode the clock receivers are
disabled too. Self Refresh Exit is performed by setting CKE asynchronously HIGH. Exit of Power
Down without Self Refresh is accomplished by setting CKE HIGH with a positive edge of CLK.
The value of CKE is latched asynchronously by Reset during Power On to determine the value of the
termination resistor of the address and command inputs.
CKE is not allowed to go LOW during a RD, a WR or a snoop burst.
Chip Select:
CS enables the command decoder when low and disables it when high. When the command decoder
is disabled, new commands with the exception of DTERDIS are ignored, but internal operations
continue. CS is one of the four command balls.
Command Inputs:
Sampled at the positive edge of CLK, CAS, RAS, and WE define (together with CS) the command
to be executed.
Data Input/Output:
The DQ signals form the 32 bit data bus. During READs the balls are outputs and during WRITEs
they are inputs. Data is transferred at both edges of RDQS.
Input Data Mask:
The DM signals are input mask signals for WRITE data. Data is masked when DM is sampled HIGH
with the WRITE data. DM is sampled on both edges of WDQS. DM0 is for DQ<0:7>, DM1 is for
DQ<8:15>, DM2 is for DQ<16:23> and DM3 is for DQ<24:31>. Although DM balls are input-only,
their loading is designed to match the DQ and WDQS balls.
Read Data Strobes:
RDQSx are unidirectional strobe signals. During READs the RDQSx are transmitted by the Graphics
SDRAM and edge-aligned with data. RDQS have preamble and postamble requirements. RDQS0 is
for DQ<0:7>, RDQS1 for DQ<8:15>, RDQS2 for DQ<16:23> and RDQS3 for DQ<24:31>.
Write Data Strobes: WDQSx are unidirectional strobe signals. During WRITEs the WDQSx are
generated by the controller and center aligned with data. WDQS have preamble and postamble
requirements. WDQS0 is for DQ<0:7>, WDQS1 for DQ<8:15>, WDQS2 for DQ<16:23> and WDQS3
for DQ<24:31>.
Bank Address Inputs:
BA select to which internal bank an ACTIVATE, READ, WRITE or PRECHARGE command is being
applied. BA are also used to distinguish between the MODE REGISTER SET and EXTENDED
MODE REGISTER SET commands.
Rev. 1.1, 2007-09
6
05292007-WAU2-UU95