HYB18H512321BF Datasheet, PDF (34/43 Pages) Qimonda AG – 512-Mbit GDDR3 Graphics RAM

Internet Data Sheet
5.12
AC Timings for HYB18H512321BF
HYB18H512321BF
512-Mbit GDDR3
Parameter CAS latency Symbol
TABLE 22
Timing Parameters for HYB18H512321BF
Limit Values
Unit Note
-8
–10
–11
–12
–14
Min Max Min. Max. Min. Max. Min. Max. Min. Max.
Clock and Clock Enable
System
frequency
CL=13
CL= 12
f_CK13
f_CK12
700 1200
450 1000
CL= 11
f_CK11
400 900
CL =10
f_CK10
400 800
CL = 9
f_CK9
400 700
CL = 8
f_CK8
400 600
CL = 7
f_CK7
400 550
Clock high level width
t_CH
0.45 0.55
Clock low-level width
t_CL
0.45 0.55
Minimum clock half period t_HP
0.45 —
Command and Address Setup and Hold Timing
—
450
400
400
400
400
400
0.45
0.45
0.45
—
1000
900
800
700
600
550
0.55
0.55
—
—
—
400
400
400
400
400
0.45
0.45
0.45
—
—
900
800
700
600
550
0.55
0.55
—
——
——
400 800
400 700
400 650
400 550
400 500
0.45 0.55
0.45 0.55
0.45 —
—
—
400
400
400
400
400
0.45
0.45
0.45
Address/Command input
t_IS
setup time
0.22 — 0.24 — 0.27 — 0.3 — 0.35
Address/Command input
t_IH
hold time
0.22 — 0.24 — 0.27 — 0.3 — 0.35
Address/Command input
t_IPW
pulse width
0.7 — 0.7 — 0.7 — 0.7 — 0.7
Mode Register Set Timing
Mode Register Set cycle time t_MRD
6
—6
—6
—6
—6
Mode Register Set to READ t_MRDR 12 — 12 — 12 — 12 — 12
timing
Row Timing
Row Cycle Time
t_RC
Row Active Time
t_RAS
ACT(a) to ACT(b) Command t_RRD
period
40 — 37 — 35 — 34 — 30
25 — 23 — 22 — 21 — 18
10 — 9 — 8 — 8 — 7
Row Precharge Time
t_RP
15 — 14 — 13 — 13 — 12
Row to Column Delay Time t_RCDRD 14 — 13 — 12 — 12 — 11
for Reads
Row to Column Delay Time t_RCDWR
for Writes
t_RCDWR(Min) = max(t_RCDRD(Min) - (WL + 1) × t_CK;2×t_CK)
Four Active Windows within t_FAW
Rank
40 — 36 — 32 — 32 — 28
—
—
700
650
600
500
450
0.55
0.55
—
—
—
—
—
—
—
—
—
—
—
—
MHz
MHz ¹⁾
MHz ¹⁾
MHz ¹⁾
MHz ¹⁾
MHz ¹⁾
MHz ¹⁾
t_CK
t_CK
t_CK ²⁾
ns
ns
t_CK
t_CK ³⁾⁴⁾
t_CK
t_CK
t_CK ⁵⁾
t_CK
t_CK
t_CK
t_CK ⁶⁾
t_CK
Rev. 1.1, 2007-09
34
05292007-WAU2-UU95