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HYB18H512321BF Datasheet, PDF (24/43 Pages) Qimonda AG – 512-Mbit GDDR3 Graphics RAM
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Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
Parameter
Symbol
Limit Values
Unit Note
Min.
Typ.
Max.
Power Supply Voltage
VDD, VDDA
1.7
1.8
1.9
V
1)3)
Power Supply Voltage for I/O Buffer
VDDQ
1.7
1.8
1.9
V
1)3)
Reference Voltage
VREF
0.69*VDDQ —
0.71*VDDQ
V
4)
Output Low Voltage
VOL(DC)
—
—
0.8
V
Input leakage current
IIL
–5.0
—
+5.0
μΑ 5)
CLK Input leakage current
IILC
–5.0
—
+5.0
μΑ
Output leakage current
IOL
–5.0
—
+5.0
μΑ 5)
1) VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
2) HYB18H512321BF–11/12/14
3) HYB18H512321BF–08/10
4) VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise
on VREF may not exceed ±2% VREF (DC). Thus, from 70% of VDDQ, VREF is allowed ± 19mV for DC error and an additional ± 27mV for AC
noise.
5) IIL and IOL are measured with ODT disabled.
5.3
DC & AC Logic Input Levels
Parameter
Symbol
TABLE 13
DC & AC Logic Input Levels (0 °C ≤ Tc ≤ 85 °C)
Limit Values
Unit Note
Min.
Max.
Input logic high voltage, DC
VIH(DC)
VREF + 0.15
—
V
1)
Input logic low voltage, DC
VIL(DC)
—
VREF -0.15
V
1)
Input logic high voltage, AC
VIH(AC)
VREF + 0.25
—
V
2)3)
Input logic low voltage, AC
VIL(AC)
—
VREF - 0.25
V
2)3)
Input logic high, DC, RESET pin
VIHR(DC)
0.65 × VDDQ
VDDQ + 0.3
V
Input logic low, DC, RESET pin
VILR(DC)
-0.3
0.35 × VDDQ
V
Input Logic High, DC, MF pin
VIHMF(DC)
VDD
VDD + 0.3
V
4)
Input Logic Low,DC, MF pin
VILMF(DC)
–0.3
0
V
1) The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to
maintain a valid level.
2) Input slew rate = 3 V/ns. If the input slew rate is less than 3 V/ns, input timing may be compromised. All slew rates are measured between
VIL(DC) and VIH(DC).
3) VIH overshoot: VIH(max) = VDDQ+0.5V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. VIL
undershoot: VIL(min) = 0 V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3 of the cycle rate.
4) The MF pin must be hard-wired on board to either VDD or VSS.
Rev. 1.1, 2007-09
24
05292007-WAU2-UU95
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