HYB18H512321BF Datasheet, PDF (33/43 Pages) Qimonda AG – 512-Mbit GDDR3 Graphics RAM

Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
Notes
1. 0 °C ≤ Tc ≤ 85 °C
2. Data Bus consists of DQ, DM, WDQS.
3. Definitions for IDD:
LOW is defined as VIN = 0.4 × VDDQ; HIGH is defined as V_IN = V_DDQ;
TABLE is defined as inputs are stable at a HIGH level.
SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and control signals,
and inputs changing 50% of each data transfer for DQ signals.
Rev. 1.1, 2007-09
33
05292007-WAU2-UU95