HYB18H512321BF Datasheet, PDF (36/43 Pages) Qimonda AG – 512-Mbit GDDR3 Graphics RAM

Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
Parameter CAS latency Symbol
Limit Values
Unit Note
-8
–10
–11
–12
–14
Min Max Min. Max. Min. Max. Min. Max. Min. Max.
Delay from AREF to next
t_RFC
ACT/ AREF
52.0 — 52.0 — 52.0 — 52.0 — 52.0 — ns
Self Refresh Exit time
t_XSC
Power Down Exit time
t_XPN
Other Timing Parameters
1000 — 1000 — 1000 — 1000 — 1000 — t_CK
7
—7
—7
—7
—6
—
t_CK
RES to CKE setup timing t_ATS
RES to CKE hold timing
t_ATH
Termination update Keep t_KO
Out timing
10 — 10 — 10 — 10 — 10 — ns
10 — 10 — 10 — 10 — 10 — ns
10 — 10 — 10 — 10 — 10 — ns
Rev. ID EMRS to DQ on
timing
t_RIDon — 20 — 20 — 20 — 20 — 20 ns
Rev. ID EMRS to DQ off
timing
t_RIDoff — 20 — 20 — 20 — 20 — 20 ns
1) DLL on mode ( -8/10/-11/-12/-14 f_CK(Min) = 400 MHz)
2) t_HP is the lesser of t_CL minimum and t_CH minimum actually applied to the device CLK, CLK inputs
3) This value of tMRD applies only to the case where the “DLL reset” bit is not activated
4) t_MRD is defined from MRS to any other command then READ
5) t_RASmax is 8×t_REF
6) t_RCDWR(Min) may not drop below 2 × t_CK
7) t_CCD is either for gapless consecutive reads or gapless consecutive writes. BL =4
8) WTR and t_WR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal
9) Please round up t_RTW to the next integer of t_CK
10) This parameter is defined per byte
Rev. 1.1, 2007-09
36
05292007-WAU2-UU95