HYB18H512321BF Datasheet, PDF (16/43 Pages) Qimonda AG – 512-Mbit GDDR3 Graphics RAM

Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
two least significant bits A0 and A1 which are set internally to the fixed value of zero each.Reserved states should not be used,
as unknown operation or incompatibility with future versions may result.
4.1.2
Burst type
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set command (A3).
This device does not support the burst interleave mode.
Burst Length
4
8
Starting Column Address
A2 A1 A0
—X X
0 XX
1 XX
Order of Accesses within a Burst
(Type = sequential)
0-1-2-3
0-1-2-3-4-5-6-7
4-5-6-7-0-1-2-3
The value applied at the balls A0 and A1 for the column address is “Don’t care”.
TABLE 8
Burst Definition
4.1.3
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit
of output data.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident
with clock edge n+m.
The two Mode Register setups support different CAS Latencies in terms of clock cycles. The mid-range-speed Mode Register
supports latencies from 7 to 14. The high-speed Mode Register supports latencies from 10 to 17. The active Mode Register
setup is selected by Bit0 of EMRS2.
4.1.4
Write Latency
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the availability of the
first bit of input data.
WL
3-4
5-6-7
TABLE 9
ON/OFF mode of DQ/DM receivers
DQ/DM-Receivers
Receivers are always on
Receivers are off and will be switched on by Write command and will be switched off again after
WL+BL
The ON/OFF state of the DQ/DM receivers depends on the Write Latency. The dependence is given in Table 9.
Rev. 1.1, 2007-09
16
05292007-WAU2-UU95