HYB18H512321BF Datasheet, PDF (22/43 Pages) Qimonda AG – 512-Mbit GDDR3 Graphics RAM

Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
4.3
Extended Mode Register 2 Set Command (EMRS2)
FIGURE 11
Extended Mode Register 2 Set Command
CLK#
CLK
CKE
CS#
RAS#
CAS#
The Extended Mode Register 2 is used to define the active
bitmap of the Mode Register and the Extended Mode
Register. The Extended Mode Register 2 must be written
after power up to operate the GDDR3 Graphics RAM. The
Extended Mode Register 2 can be programmed by
performing a normal Mode Register Set operation and setting
the BA1 bit to HIGH and BA0, BA2 bits to LOW. All bits
defined as RFU in the bitmap are reserved and must be set to
LOW. The Extended Mode Register 2 must be loaded when
all banks are idle and no burst are in progress. The controller
must wait the specified time t_MRD before initiating any
subsequent operation. The timing of the EMRS2 command
operation is equivalent to the timing of the MRS command
operation.
WE#
A0-A11
COD
BA1
1
BA0,2
0
COD: Code to be loaded into
the register
Don't Care
 
 
 






FIGURE 12
Extended Mode Register 2 Bitmap














 



 
4.3.1
App Mode
The GDDR3 Graphics RAM provides two bitmaps for the Mode Register and the Extended Mode Register respectively. The
Bitmaps are shown in the MRS and EMRS chapters.
The Bit0 of the Extended Mode Regsiter 2 defines which one of the two bitmaps is active. Bit0 set to LOW enables the mid-
range bitmap and Bit0 set to HIGH enables the High-Speed bitmap.
Rev. 1.1, 2007-09
22
05292007-WAU2-UU95