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HYB18H512321BF Datasheet, PDF (25/43 Pages) Qimonda AG – 512-Mbit GDDR3 Graphics RAM
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Internet Data Sheet
5.4
Differential Clock DC and AC Levels
HYB18H512321BF
512-Mbit GDDR3
Parameter
TABLE 14
Differential Clock DC and AC Input conditions (0 °C ≤ Tc ≤ 85 °C)
Symbol
Limit Values
Unit Note
Min.
Max.
Clock Input Mid-Point Voltage, CLK and CLK
Clock Input Voltage Level, CLK and CLK
Clock DC Input Differential Voltage, CLK and
CLK
VMP(DC)
VIN(DC)
VID(DC)
0.7 × VDDQ – 0.10
0.42
0.3
0.7 × VDDQ + 0.10 V
1)
VDDQ + 0.3
V
1)
VDDQ
V
1)
Clock AC Input Differential Voltage, CLK and CLK VID(AC) 0.5
VDDQ + 0.5
V
1)2)
AC Differential Crossing Point Input Voltage
VIX(AC)
0.7 × VDDQ – 0.15
0.7 × VDDQ + 0.15 V
1)3)
1) All voltages referenced to VSS.
2) VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
3) The value of VIX is expected to equal 0.7 × VDDQ of the transmitting device and must track variations in the DC level of the same.
5.5
Output Test Conditions
DQ
DQS
VDDQ
60 Ohm
Test point
FIGURE 13
Output Test Circuit
Rev. 1.1, 2007-09
25
05292007-WAU2-UU95
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