HYB18H512321BF Datasheet, PDF (13/43 Pages) Qimonda AG – 512-Mbit GDDR3 Graphics RAM

Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
4
Functional Description
4.1
Mode Register Set Command (MRS)
CLK#
CLK
CKE
CS#
RAS#
CAS#
WE#
A0-A11
BA0
BA1, BA2
FIGURE 2
Mode Register Set Command
The Mode Register stores the data for controlling the
operation modes of the memory. It programs CAS latency,
test mode, DLL Reset , the value of the Write Latency and the
Burst length. The Mode Register must be written after power
up to operate the SGRAM. During a ModeRegister Set
command the address inputs are sampled and stored in the
Mode Register. The Mode Register content can only be set or
changed when the chip is in Idle state. For non-READ
commands following a Mode Register Set a delay of t_MRD
must be met.
The Mode Register Bitmap is supported in two configurations.
The first configuration is intended to support the Mid-Range-
Speed application. The second configuration supports higher
clock cycles for CAS latency and is therefore prepared to
support high-speed application. The selected configuration is
defined by Bit0 of EMRS2.
COD
0
0
COD: Code to be loaded into
the register
Don't Care
Rev. 1.1, 2007-09
13
05292007-WAU2-UU95