HYB18H512321BF Datasheet, PDF (10/43 Pages) Qimonda AG – 512-Mbit GDDR3 Graphics RAM

Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
11) During Action ACTIVE an ACT command on another banks is allowed considering t_RRD . A PRE command on another bank is allowed any
time. WR, WR/A, RD and RD/A are always allowed.
12) During POWER DOWN and SELF REFRESH only the EXIT commands are allowed.
13) AUTO REFRESH starts with issuing the command and ends after t_RFC.
14) Actions MODE REGISTER SET and EXTENDED MODE REGISTER SET start with issuing the command and ends after t_MRD.
15) Action POWER DOWN EXIT starts with issuing the command and ends after t_XPN.
16) Action SELF REFRESH EXIT starts with issuing the command and ends after t_XSC.
2.4
Function Truth Table for CKE
CKE
N-1
L
L
H
CKE
n
L
H
L
CURRENT STATE
Power Down
Self Refresh
Power Down
Self Refresh
All Banks Idle
Bank(s) Active
All Banks Idle
COMMAND
X
X
DESEL or NOP
DESEL or NOP
DESEL or NOP
DESEL or NOP
Auto Refresh
TABLE 5
Function Truth Table II (CKE Table)
ACTION
Stay in Power Down
Stay in Self Refresh
Exit Power Down
Exit Self Refresh ⁵
Entry Precharge Power Down
Entry Active Power Down
Entry Self Refresh
Notes
1. CKEn is the logic step at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the GDDR3 Graphics RAM immediately prior to clock edge n.
3. COMMAND is the command registered at clock edge n, and ACTION is a result of COMMAND.
4. All states and sequences not shown are illegal or reserved.
5. DESEL or NOP commands should be issued on any clock edges occurring during the t_XSR period. A minimum of 1000 clock
cycles is required before applying any other valid command.
Rev. 1.1, 2007-09
10
05292007-WAU2-UU95