PDI1394P23 Datasheet, PDF (9/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
data bits are split into two-, four- or eight-bit parallel streams
(depending upon the indicated receive speed), resynchronized to
the local 49.152 MHz system clock and sent to the associated LLC.
The received data is also transmitted (repeated) on the other active
(connected) cable ports.
Both the TPA and TPB cable interfaces incorporate differential
comparators to monitor the line states during initialization and
arbitration. The outputs of these comparators are used by the
internal logic to determine the arbitration status. The TPA channel
monitors the incoming cable common-mode voltage. The value of
this common-mode voltage is used during arbitration to set the
speed of the next packet transmission (speed signaling). In addition,
the TPB channel monitors the incoming cable common-mode
voltage on the TPB pair for the presence of the remotely supplied
twisted-pair bias voltage (cable bias detection).
The PDI1394P23 provides a 1.86 V nominal bias voltage at the
TPBIAS terminal for port termination. The PHY contains two
independent TPBIAS circuits. This bias voltage, when seen through
a cable by a remote receiver, indicates the presence of an active
connection. This bias voltage source must be stabilized by an
external filter capacitor of 0.3 µF–1 µF.
The line drivers in the PDI1394P23 operate in a high-impedance
current mode, and are designed to work with external 112 Ω
line-termination resistor networks in order to match the 110 Ω cable
impedance. One network is provided at each end of all twisted-pair
cable connections. Each network is composed of a pair of
series-connected 56 Ω resistors. The midpoint of the pair of resistors
that is directly connected to the twisted-pair A terminals is connected
to its corresponding TPBIAS voltage terminal. The midpoint of the pair
of resistors that is directly connected to the twisted-pair B terminals is
coupled to ground through a parallel R-C network with recommended
values of 5 kΩ and 220 pF. The values of the external line termination
resistors are designed to meet the standard specifications when
connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver
output current, along with other internal operating currents. This
current setting resistor should be a low TCR part with a value of
6.34 kΩ ±1%.
When the power supply of the PDI1394P23 is removed while the
twisted-pair cables are connected, the PDI1394P23 transmitter and
receiver circuitry presents a high impedance to the cable in order to
not load the TPBIAS voltage on the other end of the cable.
When the PDI1394P23 is used with one or more of the ports not
brought out to a connector, the twisted-pair terminals of the unused
ports must be terminated for reliable operation. For each unused
port, the TPB+ and TPB– terminals can be tied together and then
pulled to ground, or the TPB+ and TPB– terminals can be connected
to the suggested termination network. The TPA+ and TPA– and
TPBIAS terminals of an unused port can be left unconnected.
The TEST0 terminal is used to set up various manufacturing test
conditions. For normal operation, it should be connected to ground.
The BRIDGE terminal is used to set the default value of the
Bridge_Aware bits in the Page 7 (Vendor Dependent) register. Tying
BRIDGE low directly (or through a 1 kΩ resistor to accommodate
other vendors’ pin-compatible chips), defaults the Bridge_Aware
field to “00” indicating a “non-bridge device.” Tying BRIDGE high,
defaults the Bridge_Aware bit to “11” indicating a “1394.1 bridge
compliant” device. Writing to the Bridge_Aware field overrides the
default setting from the BRIDGE terminal. The Bridge_Aware field is
reported in the self-ID packet at bit positions 18 and 19.
The TWOPORT terminal is used to select between one port and two
port operation. This pin should be tied high for two port operation
and tied to ground to use the PDI1394P23 as a one port PHY.
Four package terminals, used as inputs to set the default value for
four configuration status bits in the self-ID packet, should be
hard-wired high or low as a function of the equipment design. The
PC0–PC2 terminals are used to indicate the default power-class
status for the node (the need for power from the cable or the ability
to supply power to the cable). See Table 21 for power class
encoding. The C/LKON terminal is used as an input to indicate that
the node is a contender for bus manager.
The PHY supports suspend/resume as defined in the IEEE 1394a
specification. The suspend mechanism allows pairs of directly
connected ports to be placed into a low power state while
maintaining a port-to-port connection between 1394 bus segments.
While in a low power state, a port is unable to transmit or receive
data transaction packets. However, a port in a low power state is
capable of detecting connection status changes and detecting
incoming TPBIAS. When all used ports of the PDI1394P23 are
suspended, all circuits except the bias-detection circuits are
powered down, resulting in significant power savings. The TPBIAS
circuit monitors the value of incoming TPA pair common-mode
voltage when local TPBIAS is inactive. Because this circuit has an
internal current source and the connected node has a current sink,
the monitored value indicates the cable connection status. This
monitor is called connect-detect.
Both the cable bias-detect monitor and TPBIAS connect-detect
monitor are used in suspend/resume signaling and cable connection
detection. For additional details of suspend/resume operation, refer
to the 1394a specification. The use of suspend/resume is
recommended for new designs.
The port transmitter and receiver circuitry is disabled during power
down (when the PD input terminal is asserted high), during reset
(when the RESET input terminal is asserted low), when no active
cable is connected to the port, or when controlled by the internal
arbitration logic. The port twisted-pair bias voltage circuitry is
disabled during power down, during reset, or when the port is
disabled as commanded by the LLC.
The CNA (cable-not-active) terminal provides a high when there are
no twisted-pair cable ports receiving incoming bias (i.e., they are
either disconnected or suspended), and can be used along with LPS
to determine when to power-down the PDI1394P23. The CNA
output is not debounced. When the PD terminal is asserted high, the
CNA detection circuitry is enabled (regardless of the previous state
of the ports) and a pull-down is activated on the RESET terminal so
as to force a reset of the PDI1394P23 internal logic.
The LPS (link power status) terminal works with the C/LKON
terminal to manage the power usage in the node. The LPS signal
from the LLC is used in conjunction with the LCtrl bit (see Table 1
and Table 2) to indicate the active/power status of the LLC. The LPS
signal is also used to reset, disable, and initialize the PHY-LLC
interface (the state of the PHY-LCC interface is controlled solely by
the LPS input regardless of the state of the LCtrl bit).
2001 Sep 06
9