PDI1394P23 Datasheet, PDF (14/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
13.0 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITION
RΘjA Junction-to-free-air thermal resistance Board mounted, no air flow
LIMITS
UNIT
MIN
TYP MAX
—
68
—
°C/W
14.0 AC CHARACTERISTICS
SYMBOL
PARAMETER
Transmit jitter
Transmit skew
t_r
TPA, TPB differential output voltage rise time
t_f
TPA, TPB differential output voltage fall time
t_SU
Setup time, CTL0, CTL1, D0–D7, LREQ to SYSCLK
t_H
Hold time, CTL0, CTL1, D0–D7, LREQ after SYSCLK
t_D
Delay time SYSCLK to CTL0, CTL1, D0–D7
C_L
Capacitance load value CTL0, CTL1, D0–D7,
SYSCLK
C_i
Input capacitance CTL0, CTL1, D0–D7, LREQ
CONDITION
TPA, TPB
Between TPA and TPB
10% to 90%; At 1394 connector
90% to 10%; At 1394 connector
50% to 50%; See Figure 2
50% to 50%; See Figure 2
50% to 50%; See Figure 3
MIN TYP MAX UNIT
—
—
0.15
ns
—
—
0.10
ns
0.5
—
1.2
ns
0.5
—
1.2
ns
5
—
—
ns
0
—
—
ns
0.5
—
11
ns
—
10
—
pF
—
3.3
—
pF
15.0 TIMING WAVEFORMS
TPAn+
TPBn+
SYSCLK
56 Ω
TPAn–
TPBn–
SV01098
Figure 1. Test load diagram
t_D
Dn, CTLn
SV01803
Figure 3. Dn, CTLn, output delay relative to SYSCLK
SYSCLK
Dn, CTLn, LREQ
t_SU
t_H
SV01099
Figure 2. Dn, CTLn, LREQ input setup and hold times
2001 Sep 06
14