PDI1394P23 Datasheet, PDF (25/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
NOTE: The layout of the crystal portion of the PHY circuit is
important for obtaining the correct frequency, minimizing noise
introduced into the PHY’s Phase Lock Loop, and minimizing any
emissions from the circuit. The crystal and two load capacitors
should be considered as a unit during layout. The crystal and load
capacitors should be placed as close as possible to one another
while minimizing the loop area created by the combination of the
three components. Varying the size of the capacitors may help in
this. Minimizing the loop area minimizes the effect of the resonant
current (Is) that flows in this resonant circuit. This layout unit (crystal
and load capacitors) should then be placed as close as possible to
the PHY XI and XO terminals to minimize trace lengths.
It is strongly recommended that part of the verification process for
the design be to measure the frequency of the SYSCLK output of
the PHY. This should be done with a frequency counter with an
accuracy of 6 digits or better. If the SYSCLK frequency is more than
the crystal’s tolerance from 49.152 MHz, the load capacitance of the
crystal may be varied to improve frequency accuracy. If the
frequency is too high add more load capacitance; if the frequency is
too low decrease load capacitance. Typically, changes should be
done to both load capacitors (C9 and C10 above) at the same time,
and both should be of the same value. Additional design details and
requirements may be provided by the crystal vendor.
C9
C10
X1
SV01809
Figure 12. Recommended Crystal and Capacitor Layout
2001 Sep 06
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