PDI1394P23 Datasheet, PDF (23/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
17.2 RESET and Power Down
Forcing the RESET pin low resets the internal logic to the Reset
Start state and deactivates SYSCLK. Returning the RESET pin high
causes a Bus Reset condition on the active cable ports. For
power-up (and after Power Down is asserted) RESET must be
asserted low for a minimum of 2 ms from the time that the PHY
power reaches the minimum required supply voltage. This is
required to assure proper PLL operation before the PHY begins
using the clock.
The PHY must come out of RESET simultaneously or just after the
Link comes out of RESET so that the LLC/PHY handshake occurs
properly. To assure that this happens, it is recommended that the
same signal source originate LLC and PHY reset signals. If galvanic
isolation is used, an optocoupler should be used to drive the RESET
pin of the PHY. (See Philips AN2452 “IEEE 1394 bus node galvanic
isolation and power supply design”.) If galvanic isolation is not used,
the LCC and PHY reset pins should be connected directly together.
A single capacitor on the RESET pin of the PHY as described below
is recommended only in designs without an LLC device (i.e. repeater
designs).
An internal pull-up resistor is connected to V_DD, so only an external
delay capacitor is required. When using a passive capacitor on the
RESET terminal to generate a power-on reset signal, the minimum
reset time will be assured if the capacitor has a minimum value of
0.1 µF and also satisfies the following equation:
C_min = 0.0077 × T + 0.085
where C_min is the minimum capacitance on the RESET terminal in
µF, and T is the V_DD ramp time, 10%–90%, in ms.
An alternative to the passive reset is to actively drive RESET low for
the minimum reset time following power on. This input is a standard
logic Schmitt buffer and may also be driven by an open drain logic
output buffer.
The RESET pin also has an internal n-channel pull-down transistor
activated by the Power Down pin. For a reset during normal
operation, a 10 µs low pulse on this pin will accomplish a full PHY
reset. This pulse, as well as the 2 ms power up reset pulse, could be
microprocessor controlled, in which case the external delay
capacitor would not be needed. For more details on using single
capacitor isolation with this pin, please refer to the Philips Isolation
Application Note AN2452.
The Power Down input powers down all device functions with the
exception of the CNA circuit to conserve power in portable or
battery-powered applications. It must be held high for at least 2 ms
to assure a successful reset after power down.
17.3 Using the PDI1394P23 with a non-P1394a
link layer
The PDI1394P23 implements the PHY-LLC interface specified in the
P1394a Supplement. This interface is based upon the interface
described in informative Annex J of IEEE Std 1394-1995, which is the
interface used in older PHY devices. The PHY-LLC interface specified
in P1394a is completely compatible with the older Annex J interface.
The P1394a Supplement includes enhancements to the Annex J
interface that must be comprehended when using the PDI1394P23
with a non-P1394a LLC device.
• A new LLC service request was added which allows the LLC to
temporarily enable and disable asynchronous arbitration
accelerations. If the LLC does not implement this new service
request, the arbitration enhancements should not be enabled (see
the EAA bit in PHY register 5).
• The capability to perform multispeed concatenation (the
concatenation of packets of differing speeds) was added in order
to improve bus efficiency (primarily during isochronous
transmission). If the LLC does not support multispeed
concatenation, multispeed concatenation should not be enabled
in the PHY (see the EMC bit in PHY register 5).
• In order to accommodate the higher transmission speeds expected
in future revisions of the standard, P1394a extended the speed
code in bus requests from 2 bits to 3 bits, increasing the length of
the bus request from 7 bits to 8 bits. The new speed codes were
carefully selected so that new P1394a PHY and LLC devices
would be compatible, for speeds from S100 to S400, with legacy
PHY and LLC devices that use the 2-bit speed codes. The
PDI1394P23 correctly interprets both 7-bit bus requests (with 2-bit
speed code) and 8-bit bus requests (with 3-bit speed codes).
Moreover, if a 7-bit bus request is immediately followed by another
request (e.g., a register read or write request), the PDI1394P23
correctly interprets both requests. Although the PDI1394P23
correctly interprets 8-bit bus requests, a request with a speed code
exceeding S400 results in the PDI1394P23 transmitting a null
packet (data-prefix followed by data-end, with no data in the
packet).
17.4 Using the PDI1394P23 with a lower-speed
link layer
Although the PDI1394P23 is an S400 capable PHY, it may be used
with lower speed LLCs. In such a case, the LLC has fewer data
terminals than the PHY, and some Dn terminals on the PDI1394P23
will be unused. Unused Dn terminals should be pulled to ground
through 10 kΩ resistors.
The PDI1394P23 transfers all received packet data to the LLC, even
if the speed of the packet exceeds the capability of the LLC to
accept it. Some lower speed LLC designs do not properly ignore
packet data in such cases. On the rare occasions that the first 16
bits of partial data accepted by such a LLC match a node’s bus and
node ID, spurious header CRC or tcode errors may result.
In discussing this topic, the reader should be aware that the
IEEE1394a-2000 standard (paragraph 8.3.2.4.2) made the speed
maps defined in IEEE1394-1995 obsolete and defined a new field
(link_spd) in the Configuration ROM Bus_Info_Block where the
maximum speed of the node’s link layer is available. The
PDI1394P23 PHY’s default maximum speed is reported in the
self-ID packet. The IEEE1394a-2000 standard notes that bus
managers that implement the SPEED_MAP registers as specified
by IEEE Std 1394-1995 are compliant with the IEEE1394a-2000
standard but users are cautioned that the addresses utilized by
these registers may be redefined in future IEEE standards. Without
a bus manager-created and maintained speed map, in order to
transmit at the highest speed along a path, a transmitting node must
determine the node speed capability (lesser of link speed or PHY
speed) for a target node and each of the PHY speed capabilities
along the path between the source and target nodes. That is, each
node would have to create a network speed map. Some designers
may choose to implement a speed map in bus manager-capable
nodes to maximize transmission speed when a slower-than-PHY
link chip exists in a node along the transmission path. The following
paragraphs are presented for use with products that utilize speed
maps.
2001 Sep 06
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