PDI1394P23 Datasheet, PDF (20/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
17.0 APPLICATION INFORMATION
PDI1394P23
CPS
TPBIAS
390KΩ
0.3–1.0 µF
VP
CABLE
VG ^{POWER PAIR}
TPAn+
TPAn–
56Ω 56Ω
CABLE
PAIR A
CABLE PORT
TPBn+
TPBn–
56Ω 56Ω
CABLE
PAIR B
220pF
5 kΩ
OUTER SHIELD
TERMINATION
SV01821
The IEEE Std 1394–1995 calls for a 250 pF capacitor, which is a non-standard component value. A 220 pF capacitor is recommended.
Figure 4. Twisted pair cable interface connections
COMPLIANT DC-ISOLATED
OUTER SHIELD TERMINATION
1 MΩ
0.01 µF
0.1 µF
OUTER CABLE SHIELD
NON-ISOLATED
OUTER SHIELD TERMINATION
OUTER CABLE SHIELD
CHASSIS GROUND
CHASSIS GROUND
SV01748
Figure 5. Cable outer shield termination methods
0.001 µF
3 _{DGND (AGND)}
0.1 µF
V_DD
6 _{DVDD (AVDD)}
SV01805
Use one of these networks per side for all digital power and ground
pins and one per side for all analog power and ground pins. Place
the network as close to the PHY as possible.
Figure 6. Power supply decoupling network
10 kΩ
LINK POWER
LPS
SQUARE WAVE INPUT
10 kΩ
LPS
SV01806
Figure 7. Non-isolated connection variations for LPS
2001 Sep 06
20