PDI1394P23 Datasheet, PDF (4/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
4.2 LFBGA CONFIGURATION
BOTTOM (BALL) VIEW
1
2
3
4
5
6
7
8
A BCD E F GH
Ball
Signal
A1
AGND
A2
TPBIAS1
A3
TPA1–
A4
R1
A5
AGND
A6
TPBIAS0
A7
TPB0–
A8
AGND
B1
AGND
B2
AGND
B3
TPA1+
B4
TPB1–
B5
TPA0+
B6
TPA0–
B7
AGND
B8
AV_DD
Ball
Signal
C1
RESET
C2
AV_DD
C3
AV_DD
C4
TPB1+
C5
AV_DD
C6
TPB0+
C7
AV_DD
C8
TEST0
D1
PLLV_DD
D2
AV_DD
D3
PLLGND
D4
PLLV_DD
D5
R0
D6
BRIDGE
D7
TWOPORT
D8
DV_DD
Ball
Signal
E1
PLLGND
E2
XI
E3
XO
E4
D2
E5
CPS
E6
DV_DD
E7
PC1
E8
ISO
F1
DV_DD
F2
DV_DD
F3
CNA
F4
D4
F5
D6
F6
C/LKON
F7
PC0
F8
PC2
SV01909
Ball
Signal
G1
DGND
G2
DGND
G3
CTL0
G4
CTL1
G5
D5
G6
PD
G7
DGND
G8
DGND
H1
LREQ
H2
SYSCLK
H3
D0
H4
D1
H5
D3
H6
D7
H7
LPS
H8
DGND
2001 Sep 06
4