PDI1394P23 Datasheet, PDF (7/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
Name
PLLGND
PLLV_DD
Pin Type
LQFP LFBGA
I/O
Pin
Ball
Numbers Numbers
Supply
57, 58
E1, D3
—
Supply
56
D1, D4
—
R0
Bias
40
D5
—
R1
41
A4
RESET
CMOS 5V tol 53
C1
I
SYSCLK
CMOS
2
H2
O
TEST0
CMOS
29
C8
I
TPA0+,
Cable
37
B5
I/O
TPA1+
46
B3
TPA0–,
Cable
36
B6
I/O
TPA1–
45
A3
TPB0+,
Cable
35
C6
I/O
TPB1+
44
C4
TPB0–,
Cable
34
A7
I/O
TPB1–
43
B4
TPBIAS0,
Cable
38
A6
I/O
TPBIAS1
47
A2
TWOPORT
27
D7
XI
Crystal
59
E2
—
XO
60
E3
Description
PLL circuit ground terminals. These terminals should be tied together to
the low impedance circuit board ground plane.
PLL circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal are suggested, such as paralleled 0.1 µF
and 0.001 µF. This supply terminals is separated from DV_DD and AV_DD
internal to the device to provide noise isolation. They should be tied at a
low impedance point on the circuit board.
Current setting resistor pins. These pins are connected to an external
resistor to set the internal operating currents and cable driver output
currents. A resistance of 6.34 kΩ ±1% is required to meet the IEEE
1394–1995 Std. output voltage limits.
Logic reset input. Asserting this terminal low resets the internal logic. An
internal pull-up resistor to V_DD is provided so only an external
delay capacitor is required for proper power-up operation. For more
information, refer to Section 17.2. This input is otherwise a standard
Schmitt logic input, and can also be driven by an open-drain type driver.
System clock output. Provides a 49.152 MHz clock signal, synchronized
with data transfers, to the LLC.
Test control input. This input is used in manufacturing tests of the
PDI1394P23. For normal use, this terminal should be tied to GND.
Twisted-pair cable A differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector. TPA1+ and TPA1– can be left unconnected if the
TWOPORT pin is tied to DGND.
Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector. TPB1+ and TPB1– can be left unconnected if the
TWOPORT pin is tied to DGND.
Twisted-pair bias output. This provides the 1.86V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. These terminals must be decoupled with a
0.3 µF–1 µF capacitor to ground. TPBIAS1 can be left unconnected if
the TWOPORT pin is tied to DGND.
One/two port selector pin. This pin should be tied to DV_DD for two port
operation and tied to DGND for one port operation. When tied to DV_DD,
both ports 0 and 1 are operational. When tied to DGND, port 0 is
operational and port 1 is disabled.
Crystal oscillator inputs. These terminals connect to a 24.576 MHz
parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case and start supplying the external clock
before resetting the PDI1394P23). For more information, refer to
Section 17.5
2001 Sep 06
7