PDI1394P23 Datasheet, PDF (24/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
During bus initialization following a bus-reset, each PHY transmits a
self-ID packet that indicates, among other information, the speed
capability of the PHY. The bus manager (if one exists) may build a
speed-map from the collected self-ID packets. This speed-map
gives the highest possible speed that can be used on the
node-to-node communication path between every pair of nodes in
the network. However, as explained below, the speed reported in the
self-ID packet of a PDI1394P23 PHY may be adjusted to account for
a slow link chip.
In the case of a node consisting of a higher-speed PHY and a
lower-speed LLC, the speed capability of the node (lesser of the
PHY and LLC speed) is that of the lower-speed LLC. A
sophisticated bus manager can determine the LLC speed capability
by reading the configuration ROM Bus_Info_Block, or by sending
asynchronous request packets at different speeds to the node and
checking for an acknowledge; the speed-map may then be adjusted
accordingly. The speed-map should reflect that communication to
such a node must be done at the lower speed of the LLC, instead of
the higher speed of the PHY. However, speed-map entries for paths
that merely pass through the node’s PHY, but do not terminate at
that node, should not be restricted by the lower speed of the LLC.
To assist in building an accurate speed-map, the PDI1394P23 has
the capability of indicating a speed other than S400 in its transmitted
self-ID packet. This is controlled by the Link_Speed field in
register 8 of the Vendor-Dependent page (page 7). Setting the
Link_Speed field affects only the speed indicated in the self-ID
packet; it has no effect on the speed signaled to peer (adjacent
directly connected) PHYs during self-ID. The PDI1394P23 identifies
itself as S400 capable to its peers regardless of the value in the
Link_Speed field.
Generally, the Link_Speed field in register 8 of the
Vendor-Dependent page should not be changed from its power-on
default value of S400 unless it is determined that the speed-map (if
one exists) is incorrect for path entries terminating in the local node
(i.e. the node has a slower link layer chip). If the speed-map is
incorrect, it can be assumed that the bus manager has used only
the self-ID packet information to build the speed-map. In this case,
the node may update the Link_Speed field in register 8 to reflect the
lower speed capability of the LLC and then initiate another bus-reset
to cause the speed-map to be rebuilt. Note that in this scenario any
speed-map entries for node-to-node communication paths that pass
through the local node’s PHY will be restricted by the lower speed.
In the case of a leaf node (which has only one active port) the
Link_Speed field in register 8 may be set to indicate the speed of the
LLC without first checking the speed-map. Changing the
Link_Speed field in a leaf node can only affect those paths that
terminate at that node, since no other paths can pass through a leaf
node. It can have no effect on other paths in the speed-map. For
hardware configurations which can only be a leaf node (all ports but
one are unimplemented), it is recommended that the Link_Speed
field be updated immediately after power-on or hardware reset.
17.5 Crystal selection
The PDI1394P23 is designed to use an external 24.576 MHz crystal
connected between the XI and XO terminals to provide the
reference for an internal oscillator circuit. This oscillator in turn
drives a PLL circuit that generates the various clocks required for
transmission and resynchronization of data at the S100 through
S400 media data rates.
A variation of less than ±100 ppm from nominal for the media data
rates is required by IEEE Std 1394. Adjacent PHYs may therefore
have a difference of up to 200 ppm from each other in their internal
clocks, and PHYs must be able to compensate for this difference
over the maximum packet length. Larger clock variations may cause
resynchronization overflows or underflows, resulting in corrupted
packet data.
For the PDI1394P23, the SYSCLK output may be used to measure
the frequency accuracy and stability of the internal oscillator and
PLL from which it is derived. The frequency of the SYSCLK output
must be within ±100 ppm of the nominal frequency of 49.152 MHz.
The following are some typical specifications for crystals used with
the PDI1394P23 in order to achieve the required frequency
accuracy and stability:
• Crystal mode of operation: Fundamental
• Frequency tolerance at 25 °C: Total frequency variation for the
complete circuit is +100 ppm. A crystal with +30 ppm frequency
tolerance is recommended for adequate margin.
• Frequency stability (over temperature and age): A crystal with +30
ppm frequency stability is recommended for adequate margin.
NOTE: The total frequency variation must be kept below ±100 ppm
from nominal with some allowance for error introduced by board and
device variations. Trade–offs between frequency tolerance and
stability may be made as long as the total frequency variation is less
than ±100 ppm. For example, the frequency tolerance of the crystal
may be specified at 50 ppm and the temperature tolerance may be
specified at 30 ppm to give a total of 80 ppm possible variation due
to the crystal alone. Crystal aging also contributes to the frequency
variation.
• Load capacitance: For parallel resonant mode crystal circuits, the
frequency of oscillation is dependent upon the load capacitance
specified for the crystal. Total load capacitance (C_L) is a function
of not only the discrete load capacitors, but also board layout and
circuit. It may be necessary to iteratively select discrete load
capacitors until the SYSCLK output is within specification. It is
recommended that load capacitors with a maximum of "5%
tolerance be used.
As an example, for a board which uses a crystal specified for 12 pF
loading, load capacitors (C9 and C10 in Figure 11) of 16 pF each
are appropriate for the layout of that particular board. The load
specified for the crystal includes the load capacitors (C9, C10), the
loading of the PHY terminals (C_PHY), and the loading of the board
itself (C_BD). The value of C_PHY is typically about 1 pF, and C_BD is
typically 0.8 pF per centimeter of board etch; a typical board can
have 3 pF to 6 pF or more. The load capacitors C9 and C10
combine as capacitors in series so that the total load capacitance is:
C_L = [(C9 * C10) / (C9+C10)] + C_PHY + C_BD.
C9
XI
24.576 MHz
X1
ls
C10
C_PHY + C_BD
XO
SV01808
Figure 11. Load Capacitance for the PDI1394P23 PHY
2001 Sep 06
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