PDI1394P23 Datasheet, PDF (33/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
Table 20. LPS Timing Parameters
PARAMETER
DESCRIPTION
MIN MAX UNIT
T_LPSL
T_LPSH
LPS low time (when pulsed) (see Note 1)
LPS high time (when pulsed) (see Note 1)
LPS duty cycle (when pulsed) (see Note 2)
0.09 2.60 µS
0.021 2.60 µS
20
55
%
T_{LPS_RESET}
T_{LPS_DISABLE}
T_RESTORE
T_{CLK_ACTIVATE}
Time for PHY to recognize LPS deasserted and reset the interface
Time for PHY to recognize LPS deasserted and disable the interface
Time to permit optional isolation circuits to restore during an interface reset
Time for SYSCLK to be activated from reassertion of LPS
2.60 2.68 µS
26.03 26.11 µS
15
23³
µS
— 60
nS
NOTES:
1. The specified T_LPSL and T_LPSH times are worst–case values appropriate for operation with the PDI1394P23. These values are broader than
those specified for the same parameters in the P1394a Supplement (i.e., an implementation of LPS that meets the requirements of P1394a
will operate correctly with the PDI1394P23).
2. A pulsed LPS signal must have a duty cycle (ratio of T_LPSH to cycle period) in the specified range to ensure proper operation when using an
isolation barrier on the LPS signal (e.g., as shown in Figure 8)
3. The maximum value for T_RESTORE does not apply when the PHY–LLC interface is disabled, in which case an indefinite time may elapse
before LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is
deasserted for less than T_{LPS_DISABLE}.
The LLC requests that the interface be reset by deasserting the LPS
signal and terminating all bus and request activity. When the PHY
observes that LPS has been deasserted for T_{LPS_RESET}, it resets
the interface. When the interface is in the reset state, the PHY sets
its CTL and D outputs in the logic 0 state and ignores any activity on
the LREQ signal. The timing for interface reset is shown in Figure 20
and Figure 21.
(low)
ISO
(a)
(c)
SYSCLK
CTL0, CTL1
D0 – D7
(b)
LREQ
LPS
T_LPSL T_LPSH
T_{LPS_RESET}
T_RESTORE
Figure 20. Interface Reset, ISO Low
(d)
SV01810
2001 Sep 06
33