PDI1394P23 Datasheet, PDF(29/42 Page) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

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PDI1394P23 Datasheet, PDF (29/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

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Philips Semiconductors

2-port/1-port 400 Mbps physical layer interface

Preliminary data

PDI1394P23

subsequently interrupts the status transfer. Register contents are

considered to have been successfully transmitted only when all

8 bits of the register have been sent. A status transfer is retried after

being interrupted only if any status flags remain to be sent, or if a

The definition of the bits in the status transfer is shown in Table 18,

and the timing is shown in Figure 15.

The sequence of events for a status transfer is as follows:

â¢ Status transfer initiated. the PHY indicates a status transfer by

asserting status on the CTL lines along with the status data on the

D0 and D1 lines (only 2 bits of status are transferred per cycle).

Normally (unless interrupted by a receive operation), a status

transfer will be either 2 or 8 cycles long. A 2-cycle (4 bit) transfer

occurs when only status information is to be sent. An 8-cycle

(16 bit) transfer occurs when register data is to be sent in addition

to any status information.

â¢ Status transfer terminated. The PHY normally terminates a status

transfer by asserting idle on the CTL lines. If a bus reset is

pending, the PHY may also assert Grant on the CTL line

immediately following a complete status transfer.

Table 18. Status Bits

BIT(S)

NAME

0 Arbitration Reset Gap

1 Subaction gap

2 Bus reset

3 Interrupt

4â7 Address

8â15 Data

DESCRIPTION

Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as

defined in the IEEE 1394â1995 standard). This bit is used by the LLC in the busy/retry state machine.

Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in the

IEEE 1394â1995 standard). This bit is used by the LLC to detect the completion of an isochronous cycle.

Indicates that the PHY has entered the bus reset state.

Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out, a

cable-power voltage falling too low, a state time-out, or a port status change.

This field holds the address of the PHY register whose contents are being transferred to the LLC.

This field holds the register contents.

SYSCLK

CTL0, CTL1

(a)

(b)

D0, D1

S[0:1]

S[14:15]

Figure 15. Status Transfer Timing

SV01759

18.3 Receive

Whenever the PHY detects the data-prefix state on the serial bus, it

initiates a receive operation by asserting Receive on the CTL terminals

and a logic 1 on each of the D terminals (âdata-onâ indication). The

PHY indicates the start of a packet by placing the speed code

(encoded as shown in Table 19) on the D terminals, followed by

packet data. The PHY holds the CTL terminals in the Receive state

until the last symbol of the packet has been transferred. The PHY

indicates the end of packet data by asserting Idle on the CTL

terminals. All received packets are transferred to the LLC. Note that

the speed code is part of the PHY-LLC protocol and is not included in

the calculation of CRC or any other data protection mechanisms.

Table 19. Speed Code for the Receiver

D0âD7

DATA RATE

0000 0000

S100

0100 0000

S200

0101 0000

S400

1111 1111

âdata-onâ indication

It is possible for the PHY to receive a null packet, which consists of

the data-prefix state on the serial bus followed by the data-end state,

2001 Sep 06

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