PDI1394P23 Datasheet, PDF (36/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
The sequence of events for disabling the PHY-LLC interface when it
is in the differentiated mode of operation (ISO terminal is low) is as
follows:
1. Normal operation. Interface is operating normally, with LPS
active, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via
the LREQ line.
2. LPS deasserted. The LLC deasserts the LPS signal and, within 1
ms, terminates any request or interface bus activity, and places
its LREQ, CTL, and D outputs into a high-impedance state (the
LLC should terminate any output signal activity such that signals
end in a logic 0 state).
3. Interface reset. After T_{LPS_RESET} time, the PHY determines that
LPS is inactive, terminates any interface bus activity, and places
its CTL and D outputs into a high-impedance state (the PHY will
terminate any output signal activity such that signals end in a
logic 0 state). The PHY-LLC interface is now in the reset state.
4. Interface disabled. If the LPS signal remain inactive for
T_{LPS_DISABLE} time, the PHY terminates SYSCLK activity by
placing the SYSCLK output into a high-impedance state. The
PHY-LLC interface is now in the disabled state.
ISO
(high)
(a)
(c)
SYSCLK
CTL0, CTL1
D0 – D7
(b)
LREQ
LPS
T_{LPS_RESET}
T_{LPS_DISABLE}
Figure 23. Interface Disable, ISO High
(d)
SV01813
2001 Sep 06
36