PDI1394P23 Datasheet, PDF (5/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
5.0 PIN DESCRIPTION
Name
Pin Type
LQFP LFBGA
I/O
Pin
Ball
Numbers Numbers
Description
AGND
Supply
32, 33,
39, 48,
49, 50
A1, A5,
A8, B1,
B2, B7
—
Analog circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
AV_DD
Supply
30, 31,
42, 51,
52
B8, C2,
C3, C5,
C7, D2
—
Analog circuit power terminals. A combination of high frequency
decoupling capacitors on each side are suggested, such as paralleled
0.1 µF and 0.001 µF. These supply terminals are separated from
PLLV_DD and DV_DD internal to the device to provide noise isolation. They
should be tied at a low impedance point on the circuit board.
BRIDGE
CMOS
28
D6
I
BRIDGE input. This input is used to set the Bridge_Aware bits located in
the Vendor-Dependent register Page 7, base address 1001_b, bit
positions 6 and 7. This pin is sampled during a hardware reset (RESET
low). When the BRIDGE pin is tied low (or through a 1 kΩ resistor to
accommodate other vendor’s pin-compatible chips), the Bridge_Aware
bits are set to “00” indicating a “non-bridge device.” When the BRIDGE
pin is tied high, the Bridge_Aware bits are set to “11” indicating a “1394.1
bridge compliant” device. The default setting of the Bridge_Aware bits
can be overridden by writing to the register. The Bridge_Aware bits are
reported in the self-ID packet at bit positions 18 and 19.
C/LKON CMOS 5V tol 19
F6
I/O
Bus Manager/Isochronous Resource Manager (IRM) Contender
programming input and link-on output. On hardware reset, this terminal
is used to set the default value of the contender status indicated during
self-ID. Programming is done by tying the terminal through a 10-kΩ
resistor to a high (contender) or low (not contender). The resistor allows
the link-on output to override the input.
If this pin is connected to a LLC driver pin for setting Bus Manager/IRM
contender status, then a 10-kΩ series resistor should be placed on this
line between the PHY and the LLC to prevent possible contention. In this
case. the pull-high or pull-low resistors mentioned in the previous
paragraph should not be used. Refer to Figure 9.
Following hardware reset, this terminal is the link-on output, which is
used to notify the LLC to power-up and become active. The link-on
output is a square-wave signal with a period of approximately 163 ns (8
SYSCLK cycles) when active. The link-on output is otherwise driven low,
except during hardware reset when it is high impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the
LCtrl bit cleared) and when:
a) the PHY receives a link-on PHY packet addressed to this node,
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-timeout interrupt), CPSI
(cable-power-status interrupt), or STOI (state-timeout interrupt)
register bits are 1 and the RPIE (resuming-port interrupt enable)
register bit is also 1.
Once activated, the link-on output will continue active until the LLC
becomes active (both LPS active and the LCtrl bit set). The PHY also
deasserts the link-on output when a bus-reset occurs unless the link-on
output would otherwise be active because one of the interrupt bits is set
(i.e., the link-on output is active due solely to the reception of a link-on
PHY packet).
NOTE: If an interrupt condition exists which would otherwise cause the
link-on output to be activated if the LLC were inactive, the link-on output
will be activated when the LLC subsequently becomes inactive.
CNA
CMOS
3
F3
O
Cable Not Active output. This terminal is asserted high when there are
no ports receiving incoming bias voltage.
CPS
CMOS
24
E5
I
Cable Power Status input. This terminal is normally connected to cable
power through a 390 kΩ resistor. This circuit drives an internal
comparator that is used to detect the presence of cable power.
2001 Sep 06
5