PDI1394P23 Datasheet, PDF (13/42 Pages) NXP Semiconductors – 2-port/1-port 400 Mbps physical layer interface

Philips Semiconductors
2-port/1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P23
12.0 OTHER DEVICE I/O
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
See Note 1
—
81
—
mA
I_DD
Supply current
See Note 2
See Note 3
—
56
—
50
—
mA
—
mA
I_DD–PD Supply current in power down mode PD = V_DD in power down mode
—
150
—
µA
390 kΩ resistor between cable power
V_TH
Cable power status threshold voltage and CPS pin: Measured at cable power
4.7
—
side of resistor
7.5
V
V_DD = 2.7 V, I_OH = –4 mA, ISO = V_DD
2.4
—
V_OH
High-level output voltage, pins CTL0,
CTL1, D0–D7, SYSCLK, CNA
V_DD >= 3.0 V, I_OH = –4 mA, ISO = V_DD
2.8
—
Annex J: I_OH = –9 mA, ISO = 0
V_DD–0.4
—
V_OL
Low-level output voltage, pins CTL0,
CTL1, D0–D7, CNA, SYSCLK
I_OL = 4 mA, ISO = V_DD
Annex J: I_OL = 9 mA, ISO = 0
—
—
—
—
V_OH
High-level output voltage, pin C/LKON ^{VDD = 2.7 V, IOH = –4 mA; See Note 4}
2.4
V_DD >= 3.0 V, I_OH = –4 mA; See Note 4
2.7
—
—
V_OL
Low-level output voltage, pin C/LKON V_DD = 2.7 V, I_OL = 4 mA; See Note 4
—
—
I_BH+
Positive peak bus holder current, pins
CTL0, CTL1, D0–D7, LREQ
ISO = V_DD, V_I = 0 V to V_DD
0.05
—
—
V
—
V
—
V
0.4
V
0.4
V
—
V
—
V
0.3
V
1.0
mA
I_BH–
Negative peak bus holder current, pins
CTL0, CTL1, D0–D7, LREQ
ISO = V_DD, V_I = 0 V to V_DD
–1.0
—
–0.05
mA
I_I
Input current, pins LREQ, LPS, PD,
TEST0, BRIDGE, PC0–PC2
ISO = 0 V; V_DD = 3.6 V
—
—
5
µA
I_OZ
Off-state current, pins CTL0, CTL1,
D0–D7, C/LKON
VO = V_DD or 0 V
–5
—
5
µA
I_RST-UP
I_RST-DN
V_IT+
Pullup current, RESET input
Pulldown current, RESET input
Positive going threshold voltage, LREQ,
CTL0, CTL1, D0–D7 inputs
V_I = 1.5 V or 0 V
V_I = V_DD, PD = V_DD
ISO = 0 V
–90
—
.4
1.6
V_DD/2 + 0.3 —
–20
µA
2.8
mA
V_DD/2 + 0.9 V
V_IT–
Negative going threshold voltage, LREQ,
CTL0, CTL1, D0–D7 inputs
ISO = 0 V
V_DD/2 – 0.9 —
V_DD/2 – 0.3 V
V_LIT+
Positive going threshold voltage, LPS
inputs
V_LREF = 0.42 x V_DD
—
—
V_LREF+1
V
V_LIT–
Negative going threshold voltage, LPS
inputs
V_LREF = 0.42 x V_DD
V_LREF+0.2
—
—
V
V_O
TPBIAS output voltage
At rated I_O current
1.665
—
2.015
V
NOTES:
1. Transmit Max Packet (2 ports transmitting max size isochronous packet (4096 bytes), sent on every isochronous interval, S400, data value
of 0xCCCCCCCCh), V_DD = 3.3 V, T_A = 25 °C
2. Repeat typical packet (1 port receiving DV packets on every isochronous interval, 1 port repeating the packet, S100), V_DD = 3.3 V,
TA = 25 °C
3. Idle (receive cycle start on one port, transmit cycle start on other port) V_DD = 3.3 V, T_A = 25 °C
4. The C/LKON pin is able to drive an isolation circuit according to Figure 5A-20 of the IEEE-1394a-2000 standard.
2001 Sep 06
13