SAA7348GP Datasheet, PDF (54/60 Pages) NXP Semiconductors – All Compact Disc Engine ACE

Philips Semiconductors
All Compact Disc Engine (ACE)
Preliminary specification
SAA7348GP
10.3 I²S timing characteristics
V_DDD(pads) = 4.5 to 5.5 V; V_DDD(core) = 3.0 to 3.6 V; V_DDA = 3.0 to 3.6 V; V_SS = 0; T_amb = 0 to 70 °C; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I²S Timing (single speed × n); note 1; see Fig.12
CLOCK OUTPUT: SCLK (C_L = 20 pF)
T_cy(clk)
output clock period
sample rate = f_s
sample rate = 2f_s
sample rate = 4f_s
t_clkH
clock HIGH time
sample rate = f_s
sample rate = 2f_s
sample rate = 4f_s
t_clkL
clock LOW time
sample rate = f_s
sample rate = 2f_s
sample rate = 4f_s
OUTPUTS: WCLK, DATA, VALID AND DAC (C_L = 20 pF)
t_su
set-up time
sample rate = f_s
sample rate = 2f_s
sample rate = 4f_s
t_h
hold time
sample rate = f_s
sample rate = 2f_s
sample rate = 4f_s
−
472.4/n −
ns
−
236.2/n −
ns
−
118.1/n −
ns
166/n −
−
ns
83/n
−
−
ns
42/n
−
−
ns
166/n −
−
ns
83/n
−
−
ns
42/n
−
−
ns
95/n
−
−
ns
48/n
−
−
ns
24/n
−
−
ns
95/n
−
−
ns
48/n
−
−
ns
24/n
−
−
ns
Note
1. I²S timing is directly related to the over-speed factor, n, in normal operating mode;
n is replaced by the disc speed factor, d, in lock-to-disc mode.
SCLK
WCLK
DATA
DAC
VALID
1997 Jul 11
clock period Tcy(clk)
tCLKL
tCLKH
th
tsu
VDD − 0.8 V
0.8 V
VDD − 0.8 V
0.8 V
MGK505
Fig.12 I²S Timing.
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