SAA7348GP Datasheet, PDF (32/60 Pages) NXP Semiconductors – All Compact Disc Engine ACE

Philips Semiconductors
All Compact Disc Engine (ACE)
Preliminary specification
SAA7348GP
8.1.10 DATA DIRECTION REGISTERS (DDR0, DDR2 AND DDR3)
The data direction registers are used to control the direction of data flow at the port pins (P0, P2 and P3). DDR0 controls
P0; DDR2 controls P2; DDR3 controls P3. A logic 0 written to a bit makes the relevant port an input port. A logic 1 makes
it an output port. The register is byte addressable; R/W.
Table 24 Data direction registers (address DDR0: 0XFBH; DDR2: 0XFCH; DDR3: 0XFDH); note 1
7
6
Srv_frc_flock Srv_frc_lock
5
Srv_otd
4
Srv_da
3
Srv_cl
2
Srv_rab
1
Srv_startup
0
Serv_halt
Table 25 Description of DDR bits
BIT
SYMBOL
7
DDROUTX7 controls direction of PX.7
6
DDROUTX6 controls direction of PX.6
5
DDROUTX5 controls direction of PX.5
4
DDROUTX4 controls direction of PX.4
3
DDROUTX3 controls direction of PX.3
2
DDROUTX2 controls direction of PX.2
1
DDROUTX1 controls direction of PX.1
0
DDROUTX0 controls direction of PX.0
DESCRIPTION⁽¹⁾
Note to Tables 24 and 25
1. X = 0, 2 or 3, depending on register selected (DDR0, DDR2 or DDR3).
1997 Jul 11
32