SAA7348GP Datasheet, PDF (28/60 Pages) NXP Semiconductors – All Compact Disc Engine ACE

Philips Semiconductors
All Compact Disc Engine (ACE)
Preliminary specification
SAA7348GP
8.1.5 MOTOR OUTPUT QCLV REGISTER (MOQ; address 0XF2H and 0XF3H)
The Motor Output QCLV register holds the sixteen bits of the filtered (−3 dB, 300 Hz) motor error signal. This signal is
updated at a frequency of 16.537 kHz. Address 0XF3H holds the eight most significant bits, address 0XF2H the eight
least significant bits. Refreshing rule: if the low byte is read, the high byte is locked to avoid mixing up two successive
samples. If the high byte has been read, the low byte will be refreshed. The register is byte addressable; read only.
8.1.6 P3 REGISTER
The P3 register is used in the same way as in the standard 80C51. It contains a second UART, however, whose input
and output pins are R_XD1 and T_XD1 respectively. Direction control is by DDROUT3 (SFR address 0XFD; see Table 25
and Section 8.1.12). The register is bit addressable; R/W.
Table 18 P3 register (address 0XB0H to 0XB7H)
7
WRN
6
RDN
5
TXD1
4
RXD1
3
INT1
2
INT0
1
TXD0
0
RXD0
Table 19 Description of P3 register bits
BIT
SYMBOL ADDRESS
DESCRIPTION
7
WRN
0XB7H WRN
6
RDN
0XB6H WDN
5
TXD1
0XB5H TXD1: serial buffer 1; transmit
4
RXD1
0XB4H RXD1: serial buffer 1; receive
3
INT1
0XB3H INT1: external Interrupt 1
2
INT0
0XB2H INT0: external Interrupt 0
1
TXD0
0XB1H TXD0: serial buffer 0; transmit
0
RXD0
0XB0H RXD0: serial buffer 0; receive
1997 Jul 11
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