SAA7348GP Datasheet, PDF (18/60 Pages) NXP Semiconductors – All Compact Disc Engine ACE

Philips Semiconductors
All Compact Disc Engine (ACE)
Preliminary specification
SAA7348GP
Table 4 Channel status bit assignment
FUNCTION
Control
Reserved mode
Category code
Clock accuracy
Remaining
BIT
DESCRIPTION
0 to 3
copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when
copy permitted; bit 3 is logic 1 when recording has pre-emphasis
4 to 7
always zero
8 to 15
CD: bit 8 = logic 1, all other bits = logic 0
28 and 29
set by register A:
10 = class 1 crystal (<50 ppm)
00 = class 2 crystal (<1000 ppm)
01 = class 3 crystal (>1000 ppm)
16 to 27 and 30 to 191 always zero
7.6 S2B interface
This interface is in accordance with the “S2B Interface
Description”. It's a serial interface with a high level
command set for controlling a CD-ROM engine.
7.7 Audio support
Audio support consists of several parts:
• Serial data interface.
• Deemphasis control (DEEM). This signal is HIGH if the
subcode info of a track defines it to be recorded with
deemphasis.
• Kill control (KILL). This signal tests for digital silence in
the right and left channel before the digital filter.
The output is switched active LOW if silence has been
detected for at least 250 ms, if mute is active, or in
CD-ROM modes.
• Output clock for BCC-DAC applications (DACCLK).
• Oversampled output. The SAA7348 contains a
2 to 4 times oversampling IIR (Infinite
Impulse-Response) filter, and a selectable deemphasis
filter (if the de-emphasis signal is selected to come out
of DEEM then the filter is bypassed; see Table 31).
• Concealment, mute, attenuation and fade. In audio
modes a 1-sample linear interpolator becomes active if
a single sample is flagged as erroneous; left and right
channels have independent interpolators. A digital level
converter performs the following functions:
– soft mute (signal reduced to 0 in a maximum of
128 steps)
– full-scale (signal ramped back to 0 dB level)
– attenuation (signal scaled by −12 dB)
– fade (activates a 128 stage counter which allows the
signal to be scaled up or down in 0.07 dB steps)
– peak detector (measures highest audio level;
absolute level for left and right channels; the 8 MSBs
of each are output in the Q-channel data).
• Mono output selection. Either channel can be selected
to be output over both left and right channels.
7.7.1 SERIAL AUDIO DATA INTERFACE
The serial data interface can be switched between two
modes: Philips I²S and the EIAJ format.
In each case, the serial data is transferred through a 3-wire
interface. The I²S signal contains three components:
WCLK (word select), SCLK (serial clock) and DAC (serial
data). The polarity of WCLK and of the data can be
inverted.
The oversampling frequency and format are selected as
shown in Table 5. The serial data output is separate from
the CD-ROM output. In CD-ROM mode the DAC serial
data output pin will be muted.
Table 5 Oversampling frequency select
MODE
I²S
EIAJ
NUMBER
OF BITS
18
18
16
18
18
18
16
16
16
SAMPLE FREQUENCY
4f_s
2f_s
f_s
4f_s
2f_s
f_s
4f_s
2f_s
f_s
1997 Jul 11
18