SAA7348GP Datasheet, PDF (49/60 Pages) NXP Semiconductors – All Compact Disc Engine ACE

Philips Semiconductors
All Compact Disc Engine (ACE)
Preliminary specification
SAA7348GP
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
S/N
signal-to-noise ratio
−
55
−
dB
PSRR
G_tol
∆G
power supply ripple rejection at
V_DDA
gain tolerance
variation of gain between
channels
note 6
notes 2 and 7
−
45
−12
0
−
−
−
dB
+12
%
2
%
α_cs
V_offset(FTC)
channel separation
comparator FTC offset
−
60
−10
−
−
dB
+10
mV
Decoder analog front-end (V_DDD(pads) = 5.0 V; V_DDD(core) = 3.3 V; V_DDA = 3.3 V; V_SS = 0; T_amb = 25 °C)
PINS: MIDLAD, REFLCA, HFIN, REFHCA AND I_ref
f_clk
B_AGC
V_offset
G_v(AGC)
ADC clock frequency
AGC bandwidth (−3 dB)
total offset voltage
AGC gain:
range
n = 16
n = 12/16
step
V_i(AGC)(p-p))
AGC input signal range;
peak-to-peak value
V_i(ADC)
THD
S/N
input range ADC plus buffer
total harmonic distortion
signal-to-noise ratio
f_s = 5 MHz
f_s = 10 MHz
f_s = 18 MHz
Z_in
input impedance HFIN
Digital inputs
67
−
18/24
−
−7
0
−4.4
−
−
1.1
0.4
−
−
1.4
−
−36
−
−30
−
−25
−
33
−
10
−
−
+7
+12.1
−
2.3
−
−
−
−
−
−
MHz
MHz
lsb
dB
dB
V
V
dB
dB
dB
dB
kΩ
INPUT: DEFI; CMOS INPUT WITH PULL-DOWN
V_IL
LOW-level input voltage
V_IH
HIGH-level input voltage
R_pd(int)
internal pull-down resistance
C_i
input capacitance
Input: RST; CMOS input with hysteresis
V_th(r)
V_th(f)
V_hys
C_i
switching threshold rising
switching threshold falling
hysteresis voltage
input capacitance
INPUTS: RCK AND SELPLL; CMOS INPUTS
V_IL
LOW-level input voltage
V_IH
HIGH-level input voltage
I_LI
input leakage current
C_i
input capacitance
V_I = 0
V_I = 0 − V_DD
−0.3
−
0.7 × V_DD −
−
50
−
−
0.3 × V_DD V
V_DD + 0.3 V
−
kΩ
10
pF
−
0.2 × V_DD
−
−
−
−
0.33 × V_DD
−
0.8 × V_DD V
−
V
−
V
10
pF
−0.3
−
0.7 × V_DD −
−10
−
−
−
0.3 × V_DD V
V_DD + 0.3 V
+10
µA
10
pF
1997 Jul 11
49