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SAA7348GP Datasheet, PDF (52/60 Pages) NXP Semiconductors – All Compact Disc Engine ACE
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Philips Semiconductors
All Compact Disc Engine (ACE)
Preliminary specification
SAA7348GP
10.2 Subcode interface timing characteristics
VDDD(pads) = 4.5 to 5.5 V; VDDD(core) = 3.0 to 3.6 V; VDDA = 3.0 to 3.6 V; VSS = 0; Tamb = 0 to 70 °C; unless otherwise
specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Subcode interface timing (single speed × n); note 1; see Fig.11
INPUT: RCK
tclkH
tclkL
tr
tf
td(SFSY-RCK)
input clock HIGH time
input clock LOW time
input clock rise time
input clock fall time
delay time SFSY to RCK
2n--
4n--
2n--
4n--
−
−
−
−
1--n--0--
−
6n--
µs
6n--
µs
8--n--0--
ns
8--n--0--
ns
2--n--0--
µs
OUTPUTS: SBSY, SFSY AND SUB (CL = 20 pF)
Tcy(block)
block cycle time
tW(SBSY)
SBSY pulse width
Tcy(frame)
frame cycle time
tW(SFSY)
SFSY pulse width (3-wire mode only)
tSFSYH
SFSY HIGH time
tSFSYL
SFSY LOW time
td(SFSY-SUB)
delay time SFSY to SUB (P data) valid
td(RCK-SUB)
th(RCK-SUB)
delay time RCK falling to SUB
hold time RCK to SUB
1----2-n--.--0--
1----3-n--.--3--
1----4-n--.--7--
ms
−
−
3----n0---0--
µs
1----2n---2--
1----3n---6--
1----5n---0--
µs
−
−
3----6n---6--
µs
−
−
6--n--6--
µs
−
−
8--n--4--
µs
−
−
1n--
µs
−
−
0
µs
−
−
0---n-.--7-
µs
Note
1. The subcode timing is directly related to the over-speed factor, n, in normal operating mode;
n is replaced by the disc speed factor, d, in lock-to-disc mode.
1997 Jul 11
52
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