SAA7348GP Datasheet, PDF (36/60 Pages) NXP Semiconductors – All Compact Disc Engine ACE

Philips Semiconductors
All Compact Disc Engine (ACE)
8.1.14 DIGITAL PLL REGISTERS
The behaviour of the digital PLL can be monitored and
controlled using the following registers:
1. PLL Frequency Register (address 0XECH):
This register holds the 8 MSBs of the PLL frequency.
The register is byte addressable; read only.
2. PLL DC Offset Register (address 0XEDH):
This register holds the 8-bit asymmetry signal in two’s
complement form. The register is byte addressable;
read only.
3. PLL Jitter Register (address 0XEE):
This register holds the 8 MSBs of the 10 jitter bits.
The register is byte addressable; read only.
4. PLL Int Inp Register (address 0XFF):
Presets the 8 MSBs of the PLL frequency to a certain
value. The register is byte addressable; R/W.
Preliminary specification
SAA7348GP
1997 Jul 11
36