SAA7348GP Datasheet, PDF (23/60 Pages) NXP Semiconductors – All Compact Disc Engine ACE

Philips Semiconductors
All Compact Disc Engine (ACE)
Preliminary specification
SAA7348GP
8 MICROCONTROLLER INTERFACE
This section describes the microcontroller application
registers, the memory map, the decoder registers and the
servo commands.
8.1 Microcontroller applications registers
8.1.1 CLK GENERATE REGISTER (CLKgen)
The CLK generate register is used to select clock multiplier
PLL frequencies and dividers and to switch the servo clock
between single and double frequency. The register is byte
addressable; R/W.
The on-chip clock multiplier (programmable: 4×, 6× or 8×)
allows an external 8.4672 MHz crystal to be used. This
generates a single internal master clock from which all
other clock signals are derived.
Note that both the microcontroller and the servo are
designed for a 50% duty factor input clock.
For a 16× decoder speed, the internal master clock must
be 67.7376 MHz (i.e. clock multiplier set to 8×).
The 16.9344 MHz signal can be generated by setting the
clock divider to 4, resulting in a standard 50% duty factor
clock. For a 12× decoder speed, the internal master clock
must be 50.8032 MHz (i.e. clock multiplier set to 6×).
A divide factor of 3 will generate the 16.9344 MHz signal,
resulting in a 66% duty factor clock.
The clock divider values set by means of the CLKgen
register are shown in Table 9.
Table 7 CLK generate register (address 0X9EH)
7
6
5
4
CLKgen.7 CLKgen.6 CLKgen.5 clock_servohi
3
2
1
0
clock_seldiv2 clock_seldiv1 clock_selpll2 clock_selpll1
Table 8 Description of CLKgen bits
BIT
SYMBOL
DESCRIPTION
7
CLKgen.7
not used
6
CLKgen.6
5
CLKgen.5
4
clock_servohi
selects single or 2 × servo clock
3
clock_seldiv2
these bits select the clock divider for the 80C51 core and servo; see Table 9
2
clock_seldiv1
1
clock_selpll2
these bits select the clock multiplier frequency; see Table 9
0
clock_selpll1
1997 Jul 11
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