SAA7348GP Datasheet, PDF (10/60 Pages) NXP Semiconductors – All Compact Disc Engine ACE

Philips Semiconductors
All Compact Disc Engine (ACE)
Preliminary specification
SAA7348GP
7 FUNCTIONAL DESCRIPTION
The ACE combines the functionality of a DSICS
(OQ8868), a CD65 (LO9585) and an 80C51-based
microcontroller (83C654). In addition, a large part of the
glue logic has been integrated to help minimize the
number of external components required in CD-ROM
applications.
7.1 Analog front-end
The front-end circuit can be split into two parts:
1. The decoder input (HF front-end)
2. The servo input (LF front-end).
Each is powered by a separate power supply pin pair.
7.1.1 DECODER FRONT-END
The EFM signal is fed to the decoder through an ADC,
which is preceded by an AGC stage. In order to make full
use of the digital front-end resolution, the gain control
amplifier should deliver a constant 1.4 V p-p output signal.
The gain range of the AGC is 16 dB and is controlled in
steps of 1.0 dB. The gain of the variable gain amplifier is
controlled by an on-chip digital gain control block. This
block allows for both automatic and microcontroller gain
control.
The internal HF detector is sensitive to any disturbance on
the HF signal; a clean (good signal-to-noise ratio) EFM
signal is necessary since high frequency components can
disturb the HF detector. The input range of the HF
front-end varies from 2.3 V p-p down to 0.35 V p-p. If in the
lower range the signal level is between 25% and 75% of
the ADC range, the HF detector will signal NO HF (In this
range an ADC LSB translates into 5.5 mV, so half the
range equals 175 mV. If the total offset was equal to
6 LSBs, the signal range would be reduced by 2 × 33 mV.
In this case a signal of less than 109 mV would signal NO
HF). To ensure the AGC offset is minimized when the AGC
gain is high, it is necessary to connect a resistor divider to
MIDLAD, as shown in Fig.3.
The SAA7348 contains an on-chip digital equalizer and
data slicer. The equalizer is adaptive; actual equalization
depends on the disc speed. The data slicer has a
microcontroller programmable bandwidth. A fully digital
internal PLL is used to regenerate the bit clock.
The bandwidth and equalization of the PLL can be
programmed by the microcontroller. An off-track input is
necessary for certain applications. If the off-track input flag
is HIGH, the SAA7348 will assume that the servo is
following on the wrong track, and will flag all incoming HF
data as incorrect. The off-track input is connected
internally to the servo section.
handbook, halfpage
+3.3 V
VDDA1
13
820 Ω
820 Ω
MIDLAD
7
10 nF 820 Ω
VSSA1
12
MGK500
Fig.3 Front-end offset compensation.
7.1.2 SERVO FRONT END
The servo front end contains six current-input ADCs (four
for focus and two for the radial signals). The ADCs do not
require external capacitors, unlike the OQ8868 or CD7
(SAA7370). For high performance radial access, a
comparator input is available for the FTC (Fast Track
Count) signal.
The dynamic range of the ADC input currents can be
adjusted over a range dependent on the value of an
external resistor connected to I_refT. The maximum input
current for the central and satellite diodes, respectively, is
given below:
I_{i(central) (max)} = ^{2----.--4R----}_I^×-_r--_e--1_f--_T--0---⁶- ( µA)
I_{i (satellite) (max)} = ^{1----.--2R----}_I^×-_r--_e--1_f--_T--0---⁶- ( µA)
V_RH is generated internally. The value of V_RH is dependent
upon the spread of internal capacitors and on the value of
the reference current generated by the external resistor on
I_refT. Typical input currents for a range of resistance values
are given in Table 1.
1997 Jul 11
10