MN101E30N Datasheet, PDF (9/48 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101E30N/E30R/EF30R
8-bit Single-chip Microcontroller
PubNo. 2163001-019E
- Serial Interface: 6 channels
Serial 0 (Full duplex UART / Synchronous serial interface)
Synchronous serial interface
- Transfer clock source
fpll/2, fpll/4, fpll/16, fpll/64, fs/2, fs/4, Timer0,1,2,3,4 and A output, external clock
- MSB/LSB can be selected as the first bit to be transferred. An arbitrate transfer size from 1
to 8 bits can be selected.
- Sequence transmission, reception or both are available.
Full duplex UART (Baud rate timer, Timer0,1,2,3,4 and A)
- Parity check, Overrun error / Framing error detection
- Transfer size 7 to 8 bits can be selected.
Serial 1 (Full duplex UART / Synchronous serial interface)
Synchronous serial interface
- Transfer clock source
fpll/2, fpll/4, fpll/16, fpll/64, fs/2, fs/4, Timer0,1,2,3,4 and A output, external clock
- MSB/LSB can be selected as the first bit to be transferred. An arbitrate transfer size from 1
to 8 bits can be selected.
- Sequence transmission, reception or both are available.
Full duplex UART (Baud rate timer, Timer0,1,2,3,4 and A)
- Parity check, Overrun error / Framing error detection
- Transfer size 7 to 8 bits can be selected.
Serial 2 (Full duplex UART / Synchronous serial interface)
Synchronous serial interface
- Transfer clock source
fpll/2, fpll/4, fpll/16, fpll/64, fs/2, fs/4, Timer0,1,2,3,4 and A output,external clock
- MSB/LSB can be selected as the first bit to be transferred. An arbitrate transfer size from 1
to 8 bits can be selected.
- Sequence transmission, reception or both are available.
Full duplex UART (Baud rate timer, Timer0,1,2,3,4 and A)
- Parity check, Overrun error / Framing error detection
- Transfer size 7 to 8 bits can be selected.
Serial 3 (Full duplex UART / Synchronous serial interface)
Synchronous serial interface
- Transfer clock source
fpll/2, fpll/4, fpll/16, fpll/64, fs/2, fs/4, Timer0,1,2,3,4 and A output ,external clock
- MSB/LSB can be selected as the first bit to be transferred. An arbitrate transfer size from 1
to 8 bits can be selected.
Publication date: October 2015