MN101E30N Datasheet, PDF(18/48 Page) Panasonic Semiconductor

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MN101E30N Datasheet, PDF (18/48 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

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MN101E30N/E30R/EF30R

8-bit Single-chip Microcontroller

PubNo. 2163001-019E

1.3.3 Pin Functions

Table:1.3.2 Pin Functions

Name

VSS

VDD5

AVDD

AVSS

VDD18

(Capacity

1.8 V)

VDD

(Capacity

3.3 V)

OSC1

OSC2

NRST

ATRST

P00

P01

P02

P03

P04

P05

P06

P07

NO I/O

15 -

Other Function

Function

Power connect

pins

Description

Supply 2.2 V to 5.5 V to VDD5, 5.0 V to AVDD and 0 V

to VSS and AVSS.

19 -

Capacity con-

nect pins

For internal power circuit output stability, connect at

least one bypass capacitor of 1 uF or larger between

VDD18 and Vss.

20 -

Capacity con-

nect pins

For internal power circuit output stability, connect at

least one bypass capacitor of 1 uF or larger between

VDD and Vss.

(Only Flash version)

16 Input

17 Output

Clock input pins Connect these oscillation pins to ceramic or crystal

Clock output pins ocsillators for high-frequency clock operation.

If the clock is an external input, connect it to OSC1

and leave OSC2 open. The chip will not operate with

an external clock when using either the STOP or

SLOW modes.

14 Input P90

13 Output P91

Clock input pins

Clock output pins

Connect these oscillation pins to crystal oscillators for

low-frequency clock operation.

If the clock is an external input, connect it to XI and

leave XO open. the chip will not operate with an exter-

nal clock when using the STOP mode. If these pins

are not used, connect XI to VSS and leave XO open.

12 Input P27

Reset pin

[Active low]

This pin resets the chip when power is turned on, is

allocated as P27 and contains an internal pull-up

resistor (Type. 50 kïï©. Setting this pin low initialize the

internal state of the device.

Thereafter, setting the input to high releases the reset.

The hardware waits for the system clock to stabilize,

then processes the reset interrupt.

Also, if â0â is written to P27 and the reset is initiated by

software, a low level will be output. The output has an

n-channel open-drain configuration. If a capacitor is to

be inserted between NRST and VSS, it is recom-

mended that a discharge diode be placed between

NRST and VDD5.

11 input

Auto reset setting Input âHâ to enable auto reset function and âLâ to dis-

pins 2

able this function

22 I/O

RXD1A,SBI1A,TM7IOB,LED0 I/O port0

TXD1A,SBO1A,TM8IOB,LED1

SBT1A,TM9IOB,LED2

RMOUTB,TM0IOB,

TM2IOB,LED3

LED4,SBO3A,TXD3A

LED5,SBI3A,RXD3A

LED6,SBT3A

LED7,DA_A

8-bit CMOS tri-state I/O port.

Each bit can be set individually as either an input or

output by the P0DIR register. A pull-up /pull-down

resistor for each bit can be selected individually by the

P0PLUD register.

A pull-up/down resistor connection for each port can

be selected individually by the SELUD register. (How-

ever, pull-up and pull-down resistors cannot be

mixed.) Direct LED drive available at output. At reset,

the input mode is selected and pull-up resistors are

disabled (high impedance).

Publication date: October 2015

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