MN101E30N Datasheet, PDF (19/48 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101E30N/E30R/EF30R
8-bit Single-chip Microcontroller
PubNo. 2163001-019E
Name
P10
P11
P12
P13
P14
P15
P16
NO I/O
35 I/O
36
37
38
39
40
41
Other Function
SEG49,TM0IOC,RMOUTC
SEG48,TM2IOC
SEG47,TM1IOC
SEG46,TM3IOC
SEG45,TM4IOC
SEG44,TM7IOC,BUZZERB
SEG43,TM8IOC,NBUZZERB
Function
I/O port1
P20
30 I/O
SEG54,IRQ0,ACZ0
P21
31
SEG53,IRQ1,ACZ1
P22
32
SEG52,IRQ2
P23
33
SEG51,IRQ3
P24
34
SEG50,IRQ4
I/O port2
P27
12 input NRST
I/O port2
P30
42 I/O
SEG42,SBO2B,TXD2B
I/O port3
P31
43
SEG41,SBI2B,RXD2B
P32
44
SEG40,SBT2B
P33
45
SEG39,SBO4B,SDA4B
P34
46
SEG38,SBT4B,SCL4B
P35
47
SEG37,SBI4B
P36
48
SEG36
P40
49 I/O
SEG35,SBO3B,TXD3B
I/O port4
P41
50
SEG34,SBI3B,RXD3B
P42
51
SEG33,SBT3B
P43
52
SEG32,SBO0B,TXD0B
P44
53
SEG31,SBI0B,RXD0B
P45
54
SEG30,SBT0B
P46
55
SEG29,SDA5B
P47
56
SEG28,SCL5B
P50
64 I/O
SEG20,KEY0,D0,SBO0A,
I/O port5
TXD0A
P51
63
SEG21,KEY1,D1,SBI0A,
RXD0A
P52
62
SEG22,KEY2,D2,SBT0A
P53
61
SEG23,KEY3,D3,BUZZERA
P54
60
SEG24,KEY4,D4,NBUZZERA
P55
59
SEG25,KEY5,D5
P56
58
SEG26,KEY6,D6
P57
57
SEG27,KEY7,D7
P60
65 I/O
SEG19
I/O port6
P61
66
SEG18,DA_B
P62
67
SEG17,A0,TM1IOB
P63
68
SEG16,A1,TM3IOB
P64
69
SEG15,A2,TM4IOB
P65
70
SEG14,A3,SBI4A
P66
71
SEG13,A4,SBO4A,SDA4A
P67
72
SEG12,A5,SBT4A,SCL4A
Description
7-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or
output by the P1DIR register. A pull-up /pull-down
resistor for each bit can be selected individually by the
P1PLUD register.
A pull-up/down resistor connection for each port can
be selected individually by the SELUD register. A pull-
up/pull down can not be mixed. At reset, the input
mode is selected and pull-up resistors are disabled
(high impedance).
5-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or
output by the P2DIR register. A pull-up /pull-down
resistor for each bit can be selected individually by the
P2PLUD register.
A pull-up/down resistor connection for each port can
be selected individually by the SELUD register. (A
pull-up/pull down can not be mixed.) At reset, the input
mode is selected and pull-up resistors are disabled
(high impedance)
Port P27 has an N-channel open-drain configuration.
When “0” is written and the reset is initiated by soft-
ware, a low level will be output.
7-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or
output by the P3DIR register. A pull-up /pull-down
resistor for each bit can be selected individually by the
P3PLUD register.
A pull-up/down resistor connection for each port can
be selected individually by the SELUD register. (A
pull-up/pull down can not be mixed.) At reset, the input
mode is selected and pull-up resistors are disabled
(high impedance)
8-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or
output by the P4DIR register. A pull-up /pull-down
resistor for each bit can be selected individually by the
P4PLUD register.
A pull-up/down resistor connection for each port can
be selected individually by the SELUD register. A pull-
up/pull down can not be mixed. At reset, the input
mode is selected and pull-up resistors are disabled
(high impedance)
8-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or
output by the P5DIR register. A pull-up /pull-down
resistor for each bit can be selected individually by the
P5PLUD register.
A pull-up/down resistor connection for each port can
be selected individually by the SELUD register. (A
pull-up/pull down can not be mixed.) At reset, the input
mode is selected and pull-up resistors are disabled
(high impedance)
8-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or
output by the P6DIR register. A pull-up /pull-down
resistor for each bit can be selected individually by the
P6PLUD register.
A pull-up/down resistor connection for each port can
be selected individually by the SELUD register. (A
pull-up/pull down can not be mixed.) At reset, the input
mode is selected and pull-up resistors are disabled
(high impedance)
Publication date: October 2015