MN101E30N Datasheet, PDF (3/48 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101E30N/E30R/EF30R
8-bit Single-chip Microcontroller
PubNo. 2163001-019E
1.2 Hardware Functions
 Feature
- ROM Capacity:
- RAM Capacity:
508/928 KB
8 KB
- Package:
100pin LQFP (14 mm square, 0.5 mm pitch)
100pin QFP (18 mm square, 0.65 mm pitch)
- Machine Cycle:
High speed mode
0.05 ms/ 20 MHz (2.2 V to 5.5 V)
PLL mode
0.05 s/ 20 MHz (2.2 V to 5.5 V)
Low speed mode
62.5 s/16 kHz (2.2 V to 5.5 V)
- Clock Gear: Operation speed of system clock is variable by changing the frequency.
- Multiplied Clock: High-speed frequency clock (fosc) can be multiplied by 2, 3, 4, 5, 6, 8 and 10.
- Memory bank:
Data memory space is expanded by the bank system.
- Bank for the source address/Bank for the destination address.
- ROM correction: Correcting address designation: up to 7 addresses possible
- Operation Modes:
NORMAL mode ( High speed mode)
PLL mode
SLOW mode ( Low speed mode)
HALT mode
STOP mode
(The operation clock can be switched in each mode.)
- Operating Voltage:
2.2 V to 5.5 V
Publication date: October 2015