MN101E30N Datasheet, PDF (1/48 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

1.1 Overview
MN101E30N/E30R/EF30R
8-bit Single-chip Microcontroller
PubNo. 2163001-019E
1.1.1 Overview
The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C
series) incorporate multiple types of peripheral functions. This chip series is well suited for camera,
VCR, MD, TV, CD, LD, printer, telephone, home automation, pager, air conditioner, PPC, fax machine,
music instrument and other applications.
This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations
and a simple efficient instruction set. The MN101E30 series have an internal 928 KB (maximum) of
ROM and 8 KB (maximum) of RAM. Peripheral functions include 6 external interrupts, 30 internal inter-
rupts including NMI, 9 timer counters, 6 sets of serial interfaces, A/D converter, D/A converter, LCD
driver, watchdog timer, 2 sets of automatic data transfer, synchronous output function and buzzer out-
put. The configuration of this microcomputer is well suited for application as a system controller in cam-
era, timer selector for VCR, CD player, or minicomponent, and also suited for audio reproduction with a
high-precision D/A converter.
With three oscillation system (high frequency: max. 20 MHz / low frequency: 32.768 kHz and PLL: fre-
quency multiplier of high frequency) contained on the chip, the system clock can be switched to high
frequency input (high speed mode), PLL input (PLL mode), or to low frequency input (low speed mode).
The system clock is generated by dividing the oscillation clock. The best operation clock for the system
can be selected by switching its frequency by software. High speed mode has the normal mode based
on fpll/2 which is half clock generated from an original oscillation and PLL, and the double speed mode
based on fpll which is clock generated from an original oscillation without dividing.
A machine cycle (min. instructions execution) in the normal mode is 100 ns when fosc is 20 MHz (at the
time that PLL is not used). A machine cycle in the double speed mode is 50 ns when fosc is 20 MHz. A
machine cycle in the PLL mode is 50 ns (maximum).The package is 100-pin QFP, LQFP.
Publication date: October 2015