AR0130 Datasheet, PDF (7/53 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0130: 1/3-Inch CMOS Digital Image Sensor
Functional Overview
Figure 2:
provides further data path corrections and applies digital gain). The pixel data are
output at a rate of up to 74.25 Mp/s, in parallel to frame and line synchronization
signals.
Typical Configuration: Parallel Pixel Data Interface
Digital Digital
I/O core
power¹ power¹
PLL Analog Analog
power¹ power¹ power¹
VDD_IO VDD
VDD_PLL VAA VAA_PIX
Master clock
(6–50 MHz)
From
Controller
EXTCLK
SADDR
SDATA
SCLK
TRIGGER
OE_BAR
STANDBY
RESET_BAR
Reserved
DGND
VDD_IO
VDD
VDD_PLL
VAA
VAA_PIX
Digital
ground
DOUT [11:0]
PIXCLK
LINE_VALID
FRAME_VALID
To
controller
AGND
Analog
ground
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for
slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.
4. ON Semiconductor recommends that VDD_SLVS pad (only available in bare die) is left unconnected.
5. ON Semiconductor recommends that 0.1μF and 10μF decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on lay-
out and design considerations. Check the AR0130 demo headboard schematics for circuit recom-
mendations.
6. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-
pling with the digital power planes is minimized.
7. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
AR0130 DS Rev. L Pub. 6/15 EN
7
©Semiconductor Components Industries, LLC, 2015.