AR0130 Datasheet, PDF (42/53 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0130: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
I/O Timing
By default, the AR0130 launches pixel data, FV, and LV with the falling edge of PIXCLK.
The expectation is that the user captures DOUT[11:0], FV, and LV using the rising edge of
PIXCLK.
See Figure 31 and Table 9 below and Table 10 on page 43 for I/O timing (AC) characteris-
tics.
Figure 31: I/O Timing Diagram
EXTCLK
tEXTCLK
tR
tF
90%
10%
tRP
tFP
90%
10%
PIXCLK
Data[11:0]
LINE_VALID/
FRAME_VALID
tPD
tPLH
tPFH
Pxl _0
Pxl _1
FRAME_VALID leads LINE_VALID by 6 PIXCLKs.
Pxl _2
Pxl _n
tPFL
tPLL
FRAME_VALID trails
LINE_VALID by 6 PIXCLKs.
Table 9:
I/O Timing Characteristics (2.8V VDD_IO)¹
Conditions: f_PIXCLK=74.25MHz (720P60fps) VDD_IO=2.8V;
slew rate setting = 4 for PIXCLK; slew rate setting = 7 for parallel ports
Symbol Definition
Condition
Min
f_EXTCLK Input clock frequency
PLL enabled
6
t_EXTCLK Input clock period
PLL enabled
20
t_R
Input clock rise time
t_F
Input clock fall time
Input clock duty cycle
45
tJITTER2 Input clock jitter at 27 MHz
tCP
EXTCLK to PIXCLK propagation delay Nominal voltages, PLL Disabled, slew setting =4 12
tPIXCLK PIXCLK frequency²
6
t_RP
PIXCLK rise time
Slew rate setting = 4
1.60
t_FP
PIXCLK fall time
Slew rate setting = 4
1.50
PIXCLK duty cycle
PLL enabled
45
tPIXJITTER Jitter on PIXCLK
tPD
PIXCLK to Data[11:0]
PIXCLK slew rate = 4
Parallel slew rate = 7
-2.5
tPFH
PIXCLK to FV HIGH
PIXCLK slew rate = 4
Parallel slew rate = 7
-2.5
tPLH
PIXCLK to LV HIGH
PIXCLK slew rate = 4
Parallel slew rate = 7
-3.0
Typ Max Unit
50 MHz
166 ns
3
ns
3
ns
50
55
%
600
ps
20 ns
74.25 ns
2.70 7.50 ns
2.60 7.20 ns
50
55
%
1
ns
3.5 ns
0.5 ns
0.0 ns
AR0130 DS Rev. L Pub. 6/15 EN
42
©Semiconductor Components Industries, LLC, 2015.