AR0130 Datasheet, PDF (14/53 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0130: 1/3-Inch CMOS Digital Image Sensor
Output Data Format
Parallel Output Data Timing
The output images are divided into frames, which are further divided into lines. By
default, the sensor produces 968 rows of 1288 columns each. The FV and LV signals indi-
cate the boundaries between frames and lines, respectively. PIXCLK can be used as a
clock to latch the data. For each PIXCLK cycle, with respect to the falling edge, one 12-bit
pixel datum outputs on the DOUT pins. When both FV and LV are asserted, the pixel is
valid. PIXCLK cycles that occur when FV is de-asserted are called vertical blanking.
PIXCLK cycles that occur when only LV is de-asserted are called horizontal blanking.
Figure 9: Default Pixel Output Timing
PIXCLK
FV
LV
DOUT[11:0]
P0 P1 P2 P3 P4 Pn
Vertical Blanking Horiz Blanking
Valid Image Data
Horiz Blanking Vertical Blanking
LV and FV
LV Format Options
The timing of the FV and LV outputs is closely related to the row time and the frame time.
FV will be asserted for an integral number of row times, which will normally be equal to
the height of the output image.
LV will be asserted during the valid pixels of each row. The leading edge of LV will be
offset from the leading edge of FV by 6 PIXCLKs. Normally, LV will only be asserted if FV
is asserted; this is configurable as described below.
The default situation is for LV to be de-asserted when FV is de-asserted. By configuring
R0x306E[1:0], the LV signal can take two different output formats. The formats for
reading out four lines and two vertical blanking lines are shown in Figure 10.
Figure 10: LV Format Options
FV
Default
LV
FV
Continuous LV _LV
AR0130 DS Rev. L Pub. 6/15 EN
The timing of an entire frame is shown in Figure 11: “Line Timing and FRAME_VALID/
LINE_VALID Signals,” on page 15.
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