AR0130 Datasheet, PDF (49/53 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0130: 1/3-Inch CMOS Digital Image Sensor
Power-On Reset and Standby Timing
Table 19:
Power-Up Sequence
Definition
VDD_PLL to VAA/VAA_PIX³
VAA/VAA_PIX to VDD
VDD to VDD_IO
VDD_IO to VDD_SLVS
Xtal settle time
Hard Reset
Internal Initialization
PLL Lock Time
Symbol
t0
t1
t2
t3
tx
t4
t5
t6
Minimum
0
0
0⁴
0
–
1²
150000
1
Typical
10
10
10
10
30¹
–
–
–
Maximum
–
–
–
–
–
–
–
–
Unit
s
s
s
s
ms
ms
EXTCLKs
ms
Notes:
1. Xtal settling time is component-dependent, usually taking about 10 – 100 mS.
2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard
reset is held down by RC circuit, then the RC time must include the all power rail settle time and
Xtal settle time.
3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered
before or at least at the same time as the others. If the case happens that VDD_PLL is powered after
other supplies then sensor may have functionality issues and will experience high current draw on
this supply.
4. For the case where VDD_IO is 2.8V and VDD is 1.8V, it is recommended that the minimum time be
5s.
AR0130 DS Rev. L Pub. 6/15 EN
49
©Semiconductor Components Industries, LLC, 2015.