AR0130 Datasheet, PDF (32/53 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0130: 1/3-Inch CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Two-Wire Serial Register Interface
The two-wire serial interface bus enables read/write access to control and status regis-
ters within the AR0130. This interface is designed to be compatible with the electrical
characteristics and transfer protocols of the two-wire serial interface specification.
The interface protocol uses a master/slave model in which a master controls one or
more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK)
that is an input to the sensor and is used to synchronize transfers. Data is transferred
between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to
VDD_IO off-chip by a 1.5k resistor. Either the slave or master device can drive SDATA
LOW—the interface protocol determines which device is allowed to drive SDATA at any
given time.
The protocols described in the two-wire serial interface specification allow the slave
device to drive SCLK LOW; the AR0130 uses SCLK as an input only and therefore never
drives it LOW.
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of low-
level protocol elements:
1. a (repeated) start condition
2. a slave address/data direction byte
3. an (a no) acknowledge bit
4. a message byte
5. a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a
start condition, and the bus is released with a stop condition. Only the master can
generate the start and stop conditions.
Start Condition
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a “repeated start” or “restart” condition.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes.
One data bit is transferred during each SCLK clock period. SDATA can change when SCLK
is LOW and must be stable while SCLK is HIGH.
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The
default slave addresses used by the AR0130 are 0x20 (write address) and 0x21 (read
AR0130 DS Rev. L Pub. 6/15 EN
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