AR0130 Datasheet, PDF (43/53 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0130: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Table 9:
I/O Timing Characteristics (2.8V VDD_IO)¹ (continued)
Conditions: f_PIXCLK=74.25MHz (720P60fps) VDD_IO=2.8V;
slew rate setting = 4 for PIXCLK; slew rate setting = 7 for parallel ports
Symbol
tPFL
tPLL
CLOAD
CIN
Definition
PIXCLK to FV LOW
PIXCLK to LV LOW
Output load capacitance
Input pin capacitance
Condition
PIXCLK slew rate = 4
Parallel slew rate = 7
PIXCLK slew rate = 4
Parallel slew rate = 7
Min Typ Max Unit
-2.5
0.5 ns
-3.0
0.0 ns
10
pF
2.5
pF
Notes: 1. Minimum and maximum values are for the spec limits: 3.1V, -30C and 2.50V, 70C. All values are
taken at the 50% transition point.
2. Jitter from PIXCLK is already taken into account as the data of all the output parameters.
Table 10:
I/O Timing Characteristics (1.8V VDD_IO)¹
Conditions: fPIXCLK=74.25MHz (720P60fps) VDD_IO=1.8V;
slew rate setting = 4 for PIXCLK; slew rate setting = 7 for parallel ports
Symbol
f_EXTCLK
t_EXTCLK
t_R
t_F
tJITTER2
tCP
f_PIXCLK
t_RP
t_FP
tPIXJITTER
t_PD
t_PFH
t_PLH
t_PFL
t_PLL
CLOAD
CIN
Definition
Input clock frequency
Input clock period
Input clock rise time
Input clock fall time
Input clock duty cycle
Input clock jitter at 27 MHz
EXTCLK to PIXCLK propagation
delay
PIXCLK frequency²
Pixel rise time
Pixel fall time
PIXCLK duty cycle
Jitter on PIXCLK
PIXCLK to data valid
PIXCLK to FV HIGH
PIXCLK to LV HIGH
PIXCLK to FV LOW
PIXCLK to LV LOW
Output load capacitance
Input pin capacitance
Condition
Min
PLL enabled
6
PLL enabled
20
-
-
45
–
Nominal voltages, PLL Disabled, 12
slew setting =4
6
Slew rate setting = 4
2.50
Slew rate setting = 4
2.20
PLL enabled
45
PIXCLK slew rate = 4
–4.5
Parallel slew rate = 7
PIXCLK slew rate = 4
–4.0
Parallel slew rate = 7
PIXCLK slew rate = 4
–4.0
Parallel slew rate = 7
PIXCLK slew rate = 4
–4.0
Parallel slew rate = 7
PIXCLK slew rate = 4
–4.0
Parallel slew rate = 7
Typ
Max
Unit
-
50
MHz
-
166
ns
3
-
ns
3
-
ns
50
55
%
600
–
ps
20
ns
74.25
MHz
4.30
7.10
ns
3.80
6.50
ns
50
55
%
1
ns
–
2.0
ns
–
–0.5
ns
–
–0.5
ns
–
–0.5
ns
–
–0.5
ns
10
pF
2.5
pF
Notes: 1. Minimum and maximum values are for the spec limits: 1.95V, -30C and 1.70V, 70C. All values are
taken at the 50% transition point.
2. Jitter from PIXCLK is already taken into account as the data of all the output parameters.
AR0130 DS Rev. L Pub. 6/15 EN
43
©Semiconductor Components Industries, LLC, 2015.