AR0130 Datasheet, PDF (41/53 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0130: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Table 8:
Two-Wire Serial Bus Characteristics
f_{EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;}
VDD_PLL = 2.8V; T_A = 25°C
Standard-Mode
Fast-Mode
Parameter
Symbol
Min
SCLK Clock Frequency
f_SCL
0
After this period, the first clock pulse is
t_HD;STA
4.0
generated
LOW period of the SCLK clock
t_LOW
4.7
HIGH period of the SCLK clock
t_HIGH
4.0
Set-up time for a repeated START
t_SU;STA
4.7
condition
Data hold time:
t_HD;DAT
0⁴
Data set-up time
t_SU;DAT
250
Rise time of both SDATA and SCLK signals
t_r
-
Fall time of both SDATA and SCLK signals
t_f
-
Set-up time for STOP condition
t_SU;STO
4.0
Bus free time between a STOP and START
t_BUF
4.7
condition
Capacitive load for each bus line
Cb
-
Serial interface input pin capacitance
CIN_SI
-
SDATA max load capacitance
CLOAD_SD
-
SDATA pull-up resistor
RSD
1.5
Max
Min
Max
Unit
100
0
400
KHz
-
0.6
-
s
-
1.3
-
s
-
0.6
-
s
-
0.6
-
s
3.45⁵
0⁶
0.9⁵
s
-
100⁶
-
ns
1000
20 + 0.1Cb⁷
300
ns
300
20 + 0.1Cb⁷
300
ns
-
0.6
-
s
-
1.3
-
s
400
-
400
pF
3.3
-
3.3
pF
30
-
30
pF
4.7
1.5
4.7
K
Notes:
1. This table is based on I²C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I²C-compatible.
3. All values referred to V_IHmin = 0.9 VDD and V_ILmax = 0.1VDD levels. Sensor EXTCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum ^tHD;DAT has only to be met if the device does not stretch the LOW period (^tLOW) of
the SCLK signal.
6. A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement
t_{SU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch}
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
must output the next data bit to the SDATA line ^tr max + ^tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard-mode I²C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
AR0130 DS Rev. L Pub. 6/15 EN
41
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