AR0130 Datasheet, PDF (15/53 Pages) ON Semiconductor – CMOS Digital Image Sensor

AR0130: 1/3-Inch CMOS Digital Image Sensor
Output Data Format
Frame Time
The pixel clock (PIXCLK) represents the time needed to sample 1 pixel from the array.
The sensor outputs data at the maximum rate of 1 pixel per PIXCLK. One row time
(^tROW) is the period from the first pixel output in a row to the first pixel output in the
next row. The row time and frame time are defined by equations in Table 4.
Figure 11: Line Timing and FRAME_VALID/LINE_VALID Signals
FRAME_VALID
LINE_VALID
Number of pixel clocks
P1 A
Q
...
...
...
A
Q
A
P2
Table 4:
Frame Time (Example Based on 1280 x 960, 45 Frames Per Second)
Parameter
A
Name
Active data time
P1
Frame start blanking
P2
Frame end blanking
Q
Horizontal blanking
A+Q (tROW)
Line (Row) time
V
Vertical blanking
Nrows x (t_ROW)
F
Frame valid time
Total frame time
Equation
Context A: R0x3008 - R0x3004 + 1
Context B: R0x308E - R0x308A + 1
6 (fixed)
6 (fixed)
R0x300C - A
R0x300C
Context A: (R0x300A-(R0x3006-R0x3002+1)) x (A + Q)
Context B: ((R0x30AA-(R0x3090-R0x308C+1)) x (A + Q)
Context A: ((R0x3006-R0x3002+1)*(A+Q))-Q+P1+P2
Context B: ((R0x3090-R0x308C+1)*(A+Q))-Q+P1+P2
V + (Nrows x (A + Q))
Timing at 74.25 MHz
1280 pixel clocks
= 17.23s
6 pixel clocks
= 0.08s
6 pixel clocks
= 0.08s
370 pixel clocks
= 4.98s
1650 pixel clocks
= 22.22s
49,500 pixel clocks
= 666.66s
1,583,642 pixel clocks
= 21.33ms
1,633,500 pixel clocks
= 22.22ms
Sensor timing is shown in terms of pixel clock cycles (see Figure 8 on page 13). The
recommended pixel clock frequency is 74.25 MHz. The vertical blanking and the total
frame time equations assume that the integration time (coarse integration time plus fine
integration time) is less than the number of active lines plus the blanking lines:
Window Height + Vertical Blanking
(EQ 1)
If this is not the case, the number of integration lines must be used instead to determine
the frame time, (see Table 5). In this example, it is assumed that the coarse integration
time control is programmed with 2000 rows and the fine shutter width total is zero.
For Master mode, if the integration time registers exceed the total readout time, then the
vertical blanking time is internally extended automatically to adjust for the additional
integration time required. This extended value is not written back to the
frame_length_lines register. The frame_length_lines register can be used to adjust
frame-to-frame readout time. This register does not affect the exposure time but it may
extend the readout time.
AR0130 DS Rev. L Pub. 6/15 EN
15
©Semiconductor Components Industries, LLC, 2015.