SE98 Datasheet, PDF (25/39 Pages) NXP Semiconductors – DDR memory module temp sensor, 3.3 V

NXP Semiconductors
SE98
DDR memory module temp sensor, 3.3 V
9. Application design-in information
In a typical application, the SE98 behaves as a slave device and interfaces to the master
(or host) via the SCL and SDA lines. The host monitors the EVENT output pin, which is
asserted when the temperature reading exceeds the programmed values in the alarm
registers. The A0, A1 and A2 pins are directly connected to the shared SPD’s A0, A1 and
A2 pins, otherwise they must be pulled HIGH or LOW. The SDA and SCL serial interface
pins are open-drain and require pull-up resistors, and are able to sink a maximum current
of 3 mA with a voltage drop less than 0.4 V. Typical pull-up values for SCL and SDA are
10 kΩ, but the resistor values can be changed in order to meet the rise time requirement if
the capacitance load is too large due to routing, connectors, or multiple components
sharing the same bus.
slave
V_DD
SE98
A0
A1
A2
V_SS
Fig 12. Typical application
10 kΩ
(3×)
SCL
SDA
EVENT
master
HOST
CONTROLLER
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9.1 SE98 in memory module application
Figure 13 shows the SE98 being placed in the memory module application. The SE98 is
centered in the memory module to provide the function to monitor the temperature of the
DRAM. In the event of overheat, the SE98 triggers the EVENT output and the memory
controller can throttle the memory bus to slow the DRAM, or the CPU can increase the
refresh rate for the DRAM. The memory controller can also read the SE98 and watch the
DRAM thermal behavior.
DIMM
DRAM
DRAM
SE98
DRAM
DRAM
SMBus
MEMORY CONTROLLER
Fig 13. System application
EVENT
CPU
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SE98_4
Product data sheet
Rev. 04 — 2 February 2009
© NXP B.V. 2009. All rights reserved.
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